Presented on December 4, 2018 at 11:00 AM EST.
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With increasing interconnect densities, fan-out of signal line interconnects raises challenges in printed circuit board design. Microvias have become an important feature in resolving the high density interconnection challenges. In general, microvias had been demonstrated a general robust interconnect solution through development and test. However, fabrication challenges do occur and attention to the process as well as qualification is needed. Further, advances in miniaturized electronic devices have led to the evolution of microvias in high density interconnect (HDI) circuit boards from single-level to stacked structures that intersect multiple HDI layers. Stacked microvias are usually filled with electroplated copper. Challenges for fabricating reliable microvias include creating a strong interface between the base of the microvia and the target pad, and minimizing defects, such as partial filling, dimples, or voids, in the electrodeposited copper structures. Interface delamination is the most common microvia failure due to inferior quality of the electroless copper bonding between the microvia base and the target pad, while microvia fatigue life can be reduced by over 98% as a result of large voids, according to finite element analysis and fatigue life prediction.
This web seminar will examined the qualification and reliability of microvias. In addition, the influence of electroplating defects on reliability of microvias, as well as the interface delamination issue related to electroless copper will be discussed. Recommendations and guidelines will be offered for minimizing the effects of plating defects on reliability of microvias, and enabling improvement of HDI board design and process control. A method will be provided to determine the likelihood of delamination due to eletroless copper bonding.
About The Presenter
H. Azarian is a research scientist at CALCE and member of the graduate
faculty at the University of Maryland, College Park. He holds a Ph.D. in Materials
Science and Engineering from Carnegie Mellon University, a Masters degree in
Metallurgical Engineering and Materials Science from Carnegie Mellon, and a
Bachelors degree in Chemical Engineering from Princeton University.
His research focuses on the analysis, detection, prediction, and prevention
of failures in electronic systems. He has advised many organizations on reliability
of electronic products, and is the author or co-author of publications on interconnect
degradation, circuit board failure mechanisms, capacitor technology, electronic
packaging, and tribology.
Dr. Azarian is co-chair of the Miscellaneous Techniques subcommittee of the
SAE G-19A standards committee on detection of counterfeit parts. He was the
vice-chairman of the work group for IEEE Standard 1332-2012, "Reliability Program
for the Development and Production of Electronic Products," and the Technical
Editor of IEEE Standard 1624 on organizational reliability capability, for
suppliers of electronic products. He previously co-chaired iNEMI's Technology
Working Group on Sensor Technology Roadmapping.