Maxim Serebreni, DfR Solutions
Fatigue failure of solder interconnects is of high concern in high-power LED applications. Substrate coefficient of thermal expansion (CTE) in Package-on-board (PoB) LED assemblies governs the effective mismatch experienced by solder interconnects. Substrate materials such as FR4 and MCPCBs (Metal Core PCBs) influence the global CTE mismatch and subject solder joints under different thermal loads during operating conditions. Solder alloys properties (especially creep resistance) then play the key role in mitigating stress and reducing time to failure.
In this study, high power LED packages were assembled on different substrates and then subjected to power cycling. A dissipated strain energy model that takes package geometry into account was used to validate the predicted fatigue life. Smaller solder pad geometry and thermal via design resulted in lower solder joint height and provided shorter path for fatigue crack propagation. Failure analysis of the LED packages reveal fatigue cracking through the bulk of solder interconnects. The experimental data (validated by the model) also clearly shows that the creep resistant alloy provides much higher fatigue life than traditional SAC305. This paper will provide information on the contributing factors governing solder joint fatigue and validate the fatigue life prediction model for LEDs on different substrates by power cycling data.
Maxim Serebreni is a Research Engineer at DfR Solutions. He has a background in experimental mechanics, material characterization and numerical modeling. His current research involves integration of Pb-free solder alloys in harsh use environments. He has consulted in the fields of electronics reliability, electronic packaging design and solder alloy metallurgy. He is currently completing his PhD in Mechanical Engineering at the University of Maryland, College Park under the supervision of Dr. Patrick McCluskey.