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Electromigration, hot carrier injection, and time-dependent dielectric breakdown are primary die-level failure mechanisms in integrated circuits. Failure models for these mechanisms can be used to perform die-level assessment and comparison of the parts based on application load conditions. The failure models require electrical input parameters: current through interconnect, gate voltage, drain current, and dimensional input parameters: die metallization dimensions, gate oxide thickness, and effective channel length. These input parameters are unavailable in traditional documentation, such as datasheets and application notes. As a result, part users face difficulty using the failure model for part assessment. This webinar introduces the attendees to the dilemma and presents methodologies to determine electrical and dimensional input parameters. The approach to finding the input parameters combines a methodology to identify the process technology of a part with literature on process technology. The electrical input parameters are determined from transistor-level voltage-current characteristic curves provided in technical articles on process technologies, combined with part technical information from manufacturers.

About the Presenters

Rudra Vora is pursuing a Master of Science in Mechanical Engineering at the University of Maryland, College Park, MD, USA, having earned a Bachelor of Technology in Mechanical Engineering from Charotar University of Science and Technology in 2021. Currently, he is serving as a Research Assistant and working with Dr. Das at the Center of Advanced Life Cycle Engineering, University of Maryland. Rudra's research focuses on component reliability, which includes part selection and part assessment using simulation-based design of experiments on physics of failure models, sensitivity analysis, and extracting die-level information of integrated circuits parts.

Dr. Diganta Das is an Associate Research Scientist at the Center for Advanced Life Cycle Engineering. His expertise is in reliability, environmental and operational ratings of electronic parts, uprating, electronic part reprocessing, counterfeit electronics, technology trends in electronic parts, and parts selection and management methodologies. He has been the technical editor for two IEEE standards and is currently vice chair of the standards group of the IEEE Reliability Society. He is a group leader for the SAE G-19 counterfeit detection standards group.

He has been the Founding Chair of the CALCE/SMTA Counterfeit Parts and Materials Symposium since 2007. He is chair of the SAE committee developing counterfeit product detection standards. He also participates in several other SAE standard developments related to counterfeit electronics.