Bi, Hongbo (Ph.D. Mechanical Engineering)
Development Of Displacement Measurement Technique For Nano-Scale Structures
An imperative need exists for deformation data from interconnects of silicon devices. The need for nano-scale measurements becomes more urgent as the interconnect technology approaches the 50 nm node and beyond. The reliability of devices is determined largely by thermal and mechanical deformations of interconnect layers during manufacturing and operation. These are inferred by computational analysis, but informed physical analysis is vital to measure the variables and to guide and verify the computations. Deformation measurements are needed urgently in the nanometer range. What is needed is in-plane displacement measurements that are accurate within a fraction of nanometers, together with sub-micron spatial resolution.
In recent years, several techniques have been proposed to document nano-scale deformations. They include electron-beam moiré (EBM), nano-scale moiré interferometry, SEM/TEM/AFM digital image correlation (DIC), and speckle interferometry with electron microscopy (SIEM). None of the existing techniques provide both the accuracy/sensitivity (sub-nanometer) and spatial resolution (sub-micron), which are required for the analysis of nanostructures.
The objective of this thesis is to develop a new deformation measurement technique to cope with the limitations of each existing technique: A hybrid method is proposed to achieve the goal. The proposed method called Nano-Pattern Recognition and Correlation Technique (N-PRCT) uses regularly oriented nano-scale structures that are fabricated on the surface of the specimen. After obtaining the SEM pictures of patterns on the region of interest before and after loading (deformation), the conventional low-pass filter combined with a de-blur filter (Wiener Filter) are applied to eliminate the noise during SEM imaging effectively.
A unique practice of E-beam lithography is proposed and implemented to fabricate regularly oriented patterns required for the N-PRCT technique using PMMA as an E-beam resist. The proposed scheme utilizes the standard SEM for imaging to fabricate the patterns without the need of specially designed E-Beam lithography system, which makes the implementation of N-PRCT practical. Yet, the proposed procedure can produce gauge lengths (approximately 150 nm) than those produced by a commercial E-beam lithography system
The proposed method is used to determine the thermally-induced deformations of a passivation layer in a flip-chip package. The regular patterns (115 nm in diameter) are produced on the polished cross-section, and the package is subjected to a thermal loading inside SEM using a specially designed thermal conduction stage. Thermal deformations with the displacement measurement accuracy of less than 0.1 nm are obtained in a field of view of 7 μm. The results show a shear strain concentration at the interface between the passivation layer and the adjacent metal pad.
Goswami, Arindam (Ph.D. Mechanical Engineering)
Quantitative Hermeticity Assessment of Packages with Micro to Nano-Liter Cavities
Hermeticity is a measure of the “leak-proof ness” of packages with internal cavities and is critical for ensuring proper operation of the devices/circuits enclosed in them. The most widely used hermeticity detection technique in the industry is the helium fine leak test. The exiting conduction based governing equation is examined to investigate the volume dependant limits of the test when applied to metal sealed MEMS packages. The results clearly indicate that the test has limited applicability for small internal volumes (10-6 cc – 10-3 cc). The limited applicability of the guidelines specified in Method 1014.11 of the MIL-STD-883F document for hermeticity characterization is also characterized.
To cope with these limitations, a regression analysis based procedure is developed and implemented to extract the true leak rate from the apparent leak data. While the apparent leak rate obtained directly from the He mass spectrometer changes with the test parameters, the true leak rate remains constant and this can be used as a metric to evaluate a package seal.
The hermeticity of polymer sealed MEMS packages is also studied. Unlike metal sealed packages, gas transport in polymer sealed packages occurs via diffusion. A gas diffusion based model is proposed to study the hermetic behavior of these packages. An effective numerical scheme is developed to implement this model and simulate the change in cavity pressure as gas flows into or out of the cavity through the polymeric seal. An optical interferometry based leak test is developed to experimentally measure this change in cavity pressure. The experimental data is used to verify the validity of the proposed numerical scheme and the assumption of adiabatic boundary conditions made in the numerical model. An inverse method is presented to determine the two diffusion properties, diffusivity and solubility, of the polymeric seal by using the experimental data iteratively with the numerical data. The proposed method offers unique advantages over the routinely practiced/existing gas diffusion property measurement techniques.
Sanapala, Ravikumar (M.S. Mechanical Engineering)
Characterization of FR-4 Printed Circuit Board Laminates Before and After Exposure to Lead-Free Soldering Conditions
The transition to lead-free soldering of printed circuit boards
(PCBs) using solder alloys such as Sn/Ag/Cu has resulted in higher
temperature exposures during assembly compared with traditional
eutectic Sn/Pb solders. The knowledge of possible variations in the
PCB laminate material properties before and after board assembly is an
essential input in the selection of appropriate laminates.
An experimental study was conducted to investigate the effects of lead-free processing on key thermo-mechanical, physical, and chemical properties of a range of FR-4 PCB laminate materials. Laminate material properties were measured as per the IPC/ASTM/UL test standards before and after subjecting to multiple lead-free soldering cycles.
The effect of lead-free soldering conditions was observed in some of the material types and the variations in properties were related to the material constituents. Fourier transform infrared (FTIR) spectroscopy and combinatorial property analysis were performed to investigate the material-level transformations due to soldering exposures.
Plaza, Gustavo (M.S. Mechanical Engineering)
Impact of Board Pad Finish on the SNPB and Lead-Free Solder Interconnect Reliability for Leadless Chip Resistors Under Random Vibration Loading
The results from a step-stress random vibration tests are used to assess the interconnect reliability of various solder, component terminal and printed wiring board pad finishes. The durability assessment of leadless chip resistors attached with tin-lead and tin-silver-copper is examined. Component terminal finish, tin and tin-lead, in tin-lead soldered assemblies are examined. The board pad finishes used in the assemblies tested included immersion tin, immersion silver, electroless or electrolytic nickel immersed in gold, and organic solderability preservative, while tin-lead hot air solder leveling pad finish assembled with tin-lead solder served as a baseline. Destructive failure analysis is used to assess failure locations. Although the results obtained from the test indicate that under the vibration regimen studied no significant difference was found between the durability of tin-lead and tin-silver-copper assemblies, the lead-free components did outperform the tin-lead assemblies. Pad finish is found to have a greater influence on tin-lead as compared to tin-silver-copper soldered assemblies. Immersion silver and electroless or electrolytic nickel immersed in gold showed the best durability results.
Wang, Weiqiang (M.S. Mechanical Engineering)
Solder Joint Reliability of Sn and SnBi Finished and Refinished Sn (SAC/SnPb) SMT Packages under Temperature Cycling Test
Solder dip may be used as a peripheral leaded terminal refinishing process to replace the original pure tin finish with eutectic tin-lead finish or tin-silver-copper lead-free finish to mitigate tin-whisker risk. However, the reliability of solder joints formed with these refinished terminals may be different from the reliability of solder joints formed with the original pure tin finished terminals. Tin-bismuth terminal finish is another tin-whisker mitigation strategy. The reliability of solder joints formed with tin-bismuth finished terminals also needs to be determined before the implementation. The microstructure and strength of solder joints formed with refinished terminals were evaluated by comparing with those of solder joints formed with original pure tin finished terminals. The reliability of solder joints formed with original pure tin finished terminals, refinished terminals and tin-bismuth finished terminals were tested under temperature cycling. Under temperature cycling test, solder joints formed with Sn3.0Ag0.5Cu solder dipped terminals have higher reliability for thin-small-outline packages but higher reliability for 2512 resistors than those formed with the original pure tin finished terminals in both eutectic SnPb and Sn3.0Ag0.5Cu solder assembly. Solder joints formed with eutectic SnPb dipped terminals have equal reliability for thin-small-outline packages, but higher reliability for 2512 resistors than those formed with the original pure tin finished terminals when reflowed with eutectic SnPb solder. Solder joints formed with tin-bismuth finished terminals have lower reliability than original pure tin finished terminals for thin-small-outline packages for both eutectic SnPb and Sn3.0Ag0.5Cu solder assembly.
Wu, Rui (Ph.D. Mechanical Engineering)
Influence of Cryogenic Temperature and Microstructure on Fatigue Failure of Indium Solder Joint
This thesis aims to develop a fundamental understanding of the underlying mechanisms that govern indium attach degradation in applications requiring repeated excursions and extended long time dwells at temperatures below -55oC. This work was prompted by original effort of developing low temperature SiGe BiCMOS modules for Martian and Lunar exploration. Current exploration vehicles use a “warm electronic box (WEB)” to maintain the electronics in an earth-like temperature environment. This results in increasing system complexity and weight. Warm boxes also consume power and are not practical for the ~330 hour lunar night. Furthermore, intelligent nodes in a distributed system must operate in an ambient environment to monitor the health and performance of a space craft or rover, to sense the environment for scientific exploration and to act on the environment, such as to use a drill to obtain a soil sample for analysis.
Nevertheless, the reliability and life span of electronic devices systems without WEB can be significantly degraded by thermal fatigue damage as a result of wide daily temperature swings during their space exploration, when cryogenic temperatures (below -55oC) can be encountered. Attachment layer, such as die attach, solder joint and substrate attach are most inclined to fatigue damage due to the global CTE mismatch between packaging materials and their material properties at extreme cold temperatures.
With the aim of enhancing the reliability of cryogenic electronic package, indium was selected as the attachment material due to its excellent wetting capability, greater ductility and high electrical conductivity, with respect to standard PbSn solders at cryogenic temperatures. However, information on the reliability of indium attach is sparse and only concerns isothermal fatigue conditions at room temperature. No investigation has been reported on its thermal fatigue ranging from cryogenic temperature to high homologous temperatures (above room temperature), or on its isothermal fatigue behavior at cryogenic temperatures, or of the effect of microstructure evolution, in terms of intermetallics, under isothermal fatigue conditions on joint lifetime. Current lack of these fundamental understanding inhibits the assessment of the reliability of indium attach.
In this thesis, an efficient and systematic assessment was conducted to evaluate the reliability of indium attach. Constitutive properties of indium solder joint at extended low temperature were measured and the Anand constitutive model was validated for an extended temperature range, -150oC to 140oC, including extreme cold temperature. This was used to assess thermal fatigue life of indium attach. The effect of intermetallics and surface finishes on the reliability of indium attach subjected to mechanical fatigue has also been investigated. In addition, fatigue failure site, modes and mechanisms in indium attach at low temperature were identified and correlated with microstructure evolution. A fatigue model was also calibrated for indium attach at cryogenic temperatures