CALCE EPSC Graduate Student Theses (2005)

Cho, Seungmin (Ph.D. Mechanical Engineering)

Development of Moiré Interferometry for Real-time Observation of Nonlinear Thermal Deformations of Solder and Solder Assembly

An experimental apparatus using moiré interferometry is developed to characterize the thermo-mechanical behavior of solder joints. A compact moiré interferometer is combined with an environmental chamber to allow real-time observation of non-linear and time-dependent solder and solder assemblies. The first apparatus is based on convection heating and cooling to simulate an accelerated thermal cycling (ATC) condition. Vibrations caused by an environmental chamber are circumvented by unique rigid links that connect the specimen to the moiré interferometer. Displacement fields are documented while the chamber is being operated. The system is utilized to analyze thermo-mechanical behavior of a ceramic ball grid array package assembly and a plastic ball grid array package assembly. The effect of thermal cycling on the accumulated permanent deformation is documented, which reveals the temperature-dependent non-linearity of solder joints. The second apparatus is based on conduction heating and cooling to achieve a high ramp rate. A special chamber is designed and fabricated using a high power thermoelectric cooler to achieve the desired ramp rate. The system is utilized to investigate the time-dependent behavior of solder joints. A new solder joint configuration is designed and fabricated to be tested with the conduction based apparatus. The specimen is an extension of the conventional bi-material joint configuration but the unique design offers two important features; it negates the inherent shortcoming from cross sectioning required in moiré interferometry and produces a virtually uniform shear strain field at the solder joint. The deformation of solder joint is documented at a controlled ramp rate over several thermal cycles. The experimental results are analyzed and compared with those of Finite Element analysis to investigate the validity of solder constitutive models available in the literatures.

Etienne, Bevin (Ph.D. Mechanical Engineering)

The Development of Cost and Size Analysis for the Assessment of Embedded Passives in Printed Circuit Boards

Passive components are electrical components that do not provide amplification or gain. The primary functions of passive components are to manage buses, bias, decouple power and ground (bypass), filter, tune, convert, sense and protect. In 2001, passive devices accounted for 91% of all components, 41% of board area and 92% of all solder joints in an electronic system but only 2.6% were integrated in some fashion. The integrated circuit industry is achieving faster speeds by shrinking technology. This dictates that the passive solution must also shrink. In addition, the need to drive out every cent of costs, improve product reliability and the high passive to active ratios have motivated system manufacturers to consider higher levels of passive integration. These factors have increased interest in embedded passives.

This research examines the size and cost tradeoffs associated with the use of embedded passive technology for resistors and capacitors, and creates the models and methodology necessary to determine the coupled size/cost impact of embedding passives. It also examines the effects of embedding resistors on profit margin and throughput. A version of the model for performing tradeoff analyses is delivered via the CALCE Consortium and used by board manufacturers and system designers at this time. The models developed have also been used to determine the optimal number of passive devices to embed in a given system by implementing them within a Multi-Population Genetic Algorithm (MPGA). Boards from several different applications are analyzed to demonstrate the applicability of the models and the optimization approach.

The effect of board size on the optimum embedded passive solution was studied and an assessment of whether better system solutions can be found was performed. The analysis has shown that the system size limitation when embedded passives are used is not only dependent on the quantity, type, and electrical properties of the embeddable components, but is, in fact, more dependent on layout constraints associated with the placement of the non-embeddable parts. Studies indicate that the higher the embeddable passive density, the greater the probability that placement can be improved when passives are embedded.

Fang, Tong (Ph.D. Mechanical Engineering)

Tin Whisker Risk Assessment Studies

As a result of the global transition to lead (Pb)-free electronics, pure tin and high tin lead-free alloys have been widely adopted by the electronics part manufacturers as the materials of terminal finishes. However, electrically conductive tin whiskers have been found to develop in pure tin or high tin alloy finished surfaces, resulting in a reliability concern. Experimental results and observation appear to support the hypothesis that the driving forces for whisker formation is compressive stress. However, no accepted model and accelerated factors are available to describe and predict whisker growth. Though the issue of metal whiskers has been studied for over 60 years, currently there is no an industry-wide accepted methodology to quantify tin whisker risk.

In this dissertation, a tin whisker risk assessment algorithm, which mainly focuses on bridging risk, is developed. The goal of this risk assessment algorithm is to provide a practical methodology for the electronics industry to quantify the failure risks posed by tin whiskers on tin-plated electronic products. This algorithm assessES tin whisker bridging risk quantitatively as a function of time. Probabilistic and statistical methods are applied to quantify the risk parameters, such as whisker density and length, related to assess tin whisker risk. Monte Carlo technique is the basic tool to sample the whiskers and assess the bridging risk.

Two experiments are designed and conducted to simulate bridging failures caused by fixed and broken free whiskers. The methods to collect the information of the risk parameters are demonstrated. Prediction of whisker growth and tin whisker bridging risk is conducted based on the collected information. Error analyses on the differences between simulation and experimental results are provided.

Fukuda, Yuki (Ph.D. Mechanical Engineering)

Experimental Investigations of Whisker Formation on Tin Platings

With the global transition to lead-free electronics, the electronic component market has seen an increase in the selection of pure tin and tin-rich alloys as lead-free component finishes. The adoption of tin-rich finishes has enhanced a reliability issue associated with the formation of electrically conductive whiskers, emanating from tin finished surface. A spontaneous growth of whisker may bridge adjacent conductors, leading to current leakage or electrical shorts.

Whiskers tend to grow over many months. However, due to a lack of the factors accelerating whisker growth, prediction of whisker formation is extremely difficult. Therefore, the effective mitigation strategies are necessary, particularly for high-reliability applications, which require a long product operational life. The objective of this study is to investigate a method for characterizing whisker growth, which can further enable measuring the effectiveness of mitigation strategies.

Whiskers tend to grow over many months. However, due to a lack of the factors accelerating whisker growth, prediction of whisker formation is extremely difficult. Therefore, the effective mitigation strategies are necessary, particularly for high-reliability applications, which require a long product operational life. The objective of this study is to investigate a method for characterizing whisker growth, which can further enable measuring the effectiveness of mitigation strategies.

To achieve this objective, a set of experiments was conducted using matte and bright tin platings on copper, Alloy-42, and brass metal coupons. The plated coupons were subjected to high temperature exposures, including annealing (at 150oC/one hour). Whisker growth on tin-plated samples was characterized using environmental scanning electron microscopy, in terms of the maximum whisker length, length distribution, and whisker density, at different time periods up to 24 months.

Han, Changwoon (Ph.D. Mechanical Engineering)

Shadow Moiré Using Non-zero Talbot Distance and Application of Diffraction Theory to Moiré Interferometry

When shadow moiré is practiced in industry for the warpage of microelectronic devices, the required high basic measurement sensitivity limits a dynamic range due to the diffraction effect of the reference grating.  An extensive understanding of the contrast and intensity of shadow moiré fringes is required to achieve optical configurations for the measurements.  In Part I, an exact mathematical description for the contrast and intensity of shadow moiré fringe is developed using a diffraction theory for a monochromatic light source first.  The analysis is extended to study the effect of a broad spectrum light source on the contrast and intensity of shadow moiré fringes.  The effect of an aperture on the fringe contrast is defined to propose a complete expression for the contrast of shadow moiré fringe.  The mathematical analysis is exploited to define the systematic error from the non-sinusoidal intensity distribution of shadow moiré fringe when the displacement resolution is enhanced using the phase-shifting technique.  The results of the mathematical analysis provide a guideline for optimum optical configurations for the required basic measurement sensitivity, which results in a novel technique, called high sensitivity shadow moiré using non-zero Talbot distance (SM-NT).  The SM-NT increases the dynamic range substantially and allows the warpage measurements of high-end microelectronics devices, which is not possible with the conventional shadow moiré using the zero Talbot distance.

In an achromatic moiré interferometry system, a compensator grating is translated to achieve phase-shifting.  The phase-shifting in the achromatic system cannot be explained by the existing theories of moiré interferometry based on the concept of optical path length.  In Part II, a diffraction theory is used to explain the phase shifting in the achromatic system.  The results reveal that the amount of translation of the compensator grating is proportional to the diffraction order and the frequency of the compensator grating.  The diffraction theory based the mathematical description is extended further to define the mini-order diffractions associated with a general deformations.  The discrete Fourier transform is employed to characterize the mini-order from a generally deformed grating.  The results explain that the magnitude of strain is only parameter to control the angle of mini-order.

Hwang, Yu-Chul (Ph.D. Mechanical Engineering)

Electrostatic Discharge and Electrical Overstress Failures of Non-Silicon Devices

Electrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of the semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of the advanced device technologies.

This thesis provides a comprehensive understanding of ESD and EOS failures in GaAs and SiGe devices. In the first part of this thesis, characteristics of internal damage caused by several ESD test models and EOS stress in non-silicon devices (GaAs and SiGe) are identified. Failure signatures are correlated with field failures using various failure analysis techniques.

The second part of this thesis discusses the effects of ESD latent damage in GaAs devices. Depending on the stress level, ESD voltage can causes latent failures if the device is repeatedly stressed under low ESD voltage conditions, and can cause premature damage leading eventually to catastrophic failures. Electrical degradation due to ESD-induced latent damage in GaAs MESFET after cumulative low-level ESD stress is studied. Using failure analysis, combined with electrical characterization, the failure modes and signatures of EOS stressed devices with and without prior low-level ESD stress are compared.

To predict the power-to-failure level of GaAs and silicon devices, an ESD failure model using thermal RC network was developed. The correlation method of the real ESD stress and square wave pulse has been developed. The equivalent duration of square wave pulse is calculated and proposed for the HBM ESD stress. The dependence of this value on the ESD stress level and material properties is presented as well.

Mishra, Rajeev (M.S. Mechanical Engineering)

An Uprateability Risk Assessment Methodology

Uprating is a process to assess the ability of a part to meet the functionality and performance requirements of the applications in which the part is used outside the manufacturers' specification range. Uprating has emerged as a solution when the rated operating range of electronic parts does not meet the system operating temperature requirements. However, uprating can be an expensive and time consuming process. There is also no guarantee that all parts can be successfully uprated.

In 2002, some electronic part manufacturers began releasing a category of parts considered to be closer to military-grade parts, called "Enhanced Plastic (EP)". Since some of the EP parts offer wider operating temperature range compared with the commercial parts, they are promoted by the EP part manufacturers as an alternative to uprating. This thesis evaluates the EP parts and finds that when EP parts are available in wider temperature range, they can be beneficial to the electronic system manufacturers as they do not require uprating. However, the availability of EP parts in wide operating temperature range is limited and many EP parts cannot meet the functionality needs for today's electronics industry. Uprating by electronic system manufacturers remains the most common form of uprating.

This thesis evaluates the EP parts and finds that when EP parts are available in wider temperature range, they can be beneficial to the electronic system manufacturers as they do not require uprating. However, the availability of EP parts in wide operating temperature range is limited, and the cost is much higher.

The thesis then provides a priori methodology to evaluate the uprateability of an electronic part, and in particular, eliminate parts that are unlikely to be successful in uprating. Four uprateability risk levels are defined which can be determined from the available part and system information during the part selection process. The method of analyzing the information to assign the risk levels is developed for both active and passive parts.

Two case studies of uprateability risk assessment are then presented in the thesis ¨C one for an operational amplifier and the other for a polymer film capacitor. Complete analysis beginning from manufacturer and part assessment through electrical test results analysis is performed to show the uprateability risk assessment process.

Tiku, Sanjay (Ph.D. Mechanical Engineering)

Reliability Capability Evaluation for Electronics Manufacturers

In the last decade of the twentieth century, competitive and regulatory pressures have driven all types of electronics manufacturers to low-cost manufacturing, and to the evolution of a worldwide supply chain. Reliability being a risk factor associated with profit making, it is essential that reliability is managed across all tiers of the supply chain. System integrators, who are at the top of the supply chain, generally set the requirements for system reliability. However, they cannot wait until they receive the parts or sub-assemblies to assess if they are reliable. This can be an expensive iterative process. An upfront evaluation of suppliers based on their ability to meet reliability requirements can provide valuable competitive advantage.

This dissertation introduces a set of key practices that can be used to assess whether an organization has the ability to design, develop and manufacture reliable electronic products. This ability is defined in terms of a reliability capability maturity metric which is a measure of the practices within an organization that contribute to the reliability of the final product, and the effectiveness of these practices in meeting the reliability requirements of customers. In order to validate the theoretical model for reliability capability evaluation, psychometric methods based on statistical multivariate correlational analysis were used. Psychometric methods are rigorous statistical tools that are used to construct theoretical instruments which measure abstract organizational variables. The result of the analysis is a list of tasks that are critical to reliability for an electronics company. Comparative scaling factors have also been obtained empirically for reliability tasks.

The dissertation presents a procedure for evaluating and benchmarking the reliability capability of electronics companies. Five levels of maturity are defined in terms of associated reliability tasks at each level. Evaluation results are presented for reliability capability benchmarking for an electronics company as a case study. A methodology is also presented to evaluate the reliability capability of a printed circuit board (PCB) assembly manufacturer. The methodology determines the manufacturing capability of an assembler, and then evaluates the maturity of practices affecting reliability to assign a reliability capability maturity score to an assembler.

Zhao, Pin (Ph.D. Mechanical Engineering)

Creep Corrosion over Plastic Encapsulated Microcircuit Packages with Noble Metal Pre-plated Leadframes

Field failures were observed to be caused by the bridging of corrosion products across lead fingers. This phenomenon was identified as creep corrosion and was the motivation for this thesis work.

This thesis advances the state of knowledge on the creep corrosion process and the strategies for mitigation. A range of plastic encapsulated packages with noble metal pre-plated leadframes, from different vendors, with different package attributes, were selected for the study. Creep corrosion on the encapsulant surface was reproduced in an accelerated manner using mixed flowing gas (MFG) testing in laboratory conditions. Of the three most widely-used industry-standard MFG testing conditions, Telcordia Outdoor was found to be the most effective environment to induce and promote creep corrosion over the encapsulant surface; Battelle Class III environment can also induce the similar effects of creep corrosion on encapsulant surface, but in a limited rate on selective packages; Telcordia Indoor was found to induce no creep corrosion on the encapsulant materials over a 30 day test time. In both Telcordia Outdoor and Battelle Class III environments, packages attributes and applied pre-conditionings were found to have no significant influence on the creep corrosion effect.

Creep corrosion over the encapsulant surface showed a dendritic formation. The thickness of the corrosion product layer on the encapsulant tended to increase with increased exposure time. Creep corrosion products were electrically conductive and were able to bridge the adjacent leads, thereby causing electrical shorts. The corrosion products were found to consist primarily of copper oxides, copper chlorides, and copper sulfides. No distinct differences in corrosion products composition was observed on the lead versus the encapsulant surfaces. Conformal coating was identified as an effective mitigation strategy to eliminate creep corrosion on noble metal pre-plated leadframe packages.

Zheng, Yunqi (Ph.D. Mechanical Engineering)

Effect of Surface Finishes and imtermetallics on power Cycling Reliability of Snagcu Die Attach

Power semiconductor devices have been widely used in power supplies, motor control and other applications. In those applications, power semiconductor packages are required to handle significant current and dissipate relatively large amounts of heat. In additions, the packages must be capable to withstand power cycles for at least ten years of life. The solder die attach fatigue used in the packages is one of the weakest part. At the same time, industry is under the urgent demand to replace high-lead solder with lead-free solder as the new die attach materials. This dissertation is to evaluate the reliability of Sn3.5Ag0.8Cu die attach under accelerated power cycling conditions. At the same time, it has long been suspected that due to the thin bond line thickness (<100mm) of die attach, surface fishes from die and substrate side, especially intermetallic formation, will pose a high influence on reliability of die attach, which is also investigated here.

First, the effect of five types of PCB (printing circuit board) finishes on reliability Sn3.8Ag0.7Cu solder joint under high temperature aging was evaluated through microstructure characterization and shear testing. Dissolution of Cu or Ag from plating systems during soldering is critical to form large u6Sn5 or Ag3Sn in the bulk. Solder joints on all the lead-free finishes has shown satisfactory bonding and no interfacial weakness due to intermetallics related has occurred. The study also confirmed that intermetallic failure is more susceptible under high strain rate.

The main part of the dissertation is to evaluate power-cycled reliability of Sn3.5Ag0.8Cu die attach in power MOSFET packages, through accelerated power cycling test, failure analysis, thermal transient analysis and thermo-mechanical fatigue modeling. In the experiments, die tilt was observed and die attach crack always occurred at thicker side. Microstructure characterization has further determined that microstructure of die attach changes with thickness, especially effect of Ag3Sn formed due to the dissolution of Ag from die finishes. On the other hand, thermo-mechanical simulation based homogenous properties of the solder have determined that thicker side is under lower stress/strain than the thinner side. It is believed that thinner bond line is more resistant to fatigue due to more uniform microstructure and intermetallic distribution.

In the first step of thermo-mechanical simulation, 3D thermal transient analysis was used to determine the temperature profile of the power module. The analysis has correlated increase in the thermal impedance to crack propagation and determined that crack initiation is the limiting process under power cycling. In the second step, 2D diagonal plain-strain structural model, considering plasticity and creep properties of the SnAgCu solder, was developed to evaluate the deformation in the die attach. At last, the critical area used in energy partitioning model to evaluate die attach fatigue life is calibrated by experimental results.

Clearly, intermetallic formation does not introduce new failure mechanisms to SnAgCu die attach/solder joint, even with large Ag3Sn (or Cu6Sn5) aggregates due to dissolution of Ag or Cu from interfaces. However, as thickness of die attach decreases to around 30mm, thermo-mechanical fatigue properties of the solder changes with thickness and effect of surface finishes as well as interfaces need to be considered.