CALCE EPSC Graduate Student Theses (2004)

Blattau, Nathan J. (Ph.D. Mechanical Engineering)

Models For Rapid Assessment of Surface Mount Component Failures During Printed Wiring Board Bending

Manufactures are forced to adopt smaller leadless surface mount type electronic components as the demand for more complex and denser electronics increases. The old style leaded components are simply too large and cannot meet the Input/Output demands of some of the latest electronic devices. These leads that once served to ease manufacturing and accommodate thermally induced mismatches are no longer necessary. However, elimination of the leads on a component yields a much stiffer assembly. This added stiffness has shifted some of the focus from thermal-mechanically induced failures to failures due to printed wiring board bending.

The typical printed wiring board (PWB) is constructed from FR-4 glass epoxy materials and is quite compliant and therefore susceptible to significant amounts of bending under various loading conditions. Loads producing this bending can be generated throughout the life of the PWB and are transferred to the components generating considerable stresses inside the component and its attaching structures. Failures that result from these stresses usually manifest themselves in the body or the attach structure of the component as cracks. Finite element modeling is a very useful tool in predicting stresses and can yield very accurate results but can be time consuming. The speed at which new products must be developed severely limits the time designers have to evaluate their designs. They must be able to rapidly determine if the components used can survive these curvature-induced stresses.

Current analytical approaches to rapidly predict the stresses in components due to printed wiring board bending have been limited to specific components and geometries. Other limitations occur when describing the material properties of the component. The need for an approach that can handle a wide range of component styles and geometries is clearly evident.

The proposed approach is to use the stiffness method in conjunction with CalcePWA software and commercial finite element analysis software to generate more capable stress analysis models for rapidly assessing the durability of surface mount components during printed wiring board bending. The durability of the component will be determined by finding the various overstress limits for the materials used in its construction through experimental data and finite element analysis. CalcePWA will be used to attain the printed wiring board curvatures for the applied loading conditions. These curvatures will be converted into the moments applied to the component. The stiffness method or analytical models will then be used to convert the applied moment into the forces and moments seen in the various parts of the component. Converting these loads to stresses and comparing them to the previously attained overstress limits will determine whether the component has failed and where the failure is located.

Donahoe, Daniel (Ph.D. Mechanical Engineering)

Moisture in Multilayer Ceramic Capacitors

When both precious metal and base metal electrode (BME) EIA 0805 capacitors were subjected to autoclave (120 oC/100 % RH) testing, it was found that the precious metal capacitors aged according to the well known aging mechanism (less than 3 % from their starting values), but the BME capacitors degraded to below the -30% criterion at 500 hours of exposure. The reasons for this new failure mechanism are complex, and there were two theories that were hypothesized. The first was that there could be oxidation or corrosion of the nickel plates. The other hypothesis was that the loss of capacitance was due to molecular changes in the barium titanate. This thesis presents the evaluation of these hypotheses and the physics of the degradation mechanism. It is concluded that the continuous reduction in capacitor size makes the newer BME capacitors more vulnerable to moisture degradation than the older generation precious metal capacitors. In addition, standard humidity life testing, such as JESD-22 THB and HAST, will likely not uncover this problem. Therefore, poor reliability due to degradation of BME multilayer ceramic capacitors may catch manufacturers and consumers by surprise.

Ganesan, Sathyanarayan (M.S. Mechanical Engineering)

Virtual Design and Improved System Level Approach for Life Consumption Monitoring of Electronics

Health and life consumption monitoring has emerged as a promising alternative to traditional reliability prediction, scheduled maintenance, and run-to-failure operations. A product¡¯s health is the extent of degradation or deviation from its "normal" operating state. Hence health monitoring is based on the condition of the actual system or equipment concerned, not on the statistical mean. By determining whether and, more importantly, when failure can occur, procedures can be developed to mitigate, manage or maintain the product. Life consumption monitoring (LCM) a prognostic method to assess product reliability based on its remaining life in a given life cycle environment.

This thesis presents an improved version of the life consumption monitoring process. The life consumption monitoring process includes failure modes, mechanisms and effects analysis (FMMEA), virtual reliability assessment, monitoring product parameters, data simplification, stress and damage accumulation analysis and remaining life estimation. A new process flow for conducting FMMEA is developed and documented. Also a methodology for selection of critical failure mechanisms and the determining the environmental and operational parameters to be monitored has been developed and documented. Criteria for selection of prognostic techniques and uncertainty issues associated with remaining life predictions have been explained. Software for the life consumption monitoring process has been developed and has been validated with the results of previously conducted case study.

Hwang, Yu-Chul (Ph.D. Mechanical Engineering)

Electrostatic Discharge and Electrical Overstress Failures of Non-Silicon Devices

Electrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of the semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of the advanced device technologies.

This thesis provides a comprehensive understanding of ESD and EOS failures in GaAs and SiGe devices. In the first part of this thesis, characteristics of internal damage caused by several ESD test models and EOS stress in non-silicon devices (GaAs and SiGe) are identified. Failure signatures are correlated with field failures using various failure analysis techniques.

The second part of this thesis discusses the effects of ESD latent damage in GaAs devices. Depending on the stress level, ESD voltage can causes latent failures if the device is repeatedly stressed under low ESD voltage conditions, and can cause premature damage leading eventually to catastrophic failures. Electrical degradation due to ESD-induced latent damage in GaAs MESFET after cumulative low-level ESD stress is studied. Using failure analysis, combined with electrical characterization, the failure modes and signatures of EOS stressed devices with and without prior low-level ESD stress are compared.

To predict the power-to-failure level of GaAs and silicon devices, an ESD failure model using thermal RC network was developed. The correlation method of the real ESD stress and square wave pulse has been developed. The equivalent duration of square wave pulse is calculated and proposed for the HBM ESD stress. The dependence of this value on the ESD stress level and material properties is presented as well.

Li, Lin (Ph.D. Mechanical Engineering)

Analysis and Mitigation of Electromagnetic Noise in Resonant Cavities and Apertures

The trend of low voltage in electronics circuits and boards makes them vulnerable to electromagnetic interference (EMI). Furthermore, higher speed (clock rate) leads to faster switching which increases the potential for higher radiation from circuits and boards. These inevitable trends collectively compromise the electromagnetic compatibility of electronic systems by increasing their electromagnetic immunity and susceptibility. In this work, radiation from enclosures and apertures is studies and characterized and radiation mitigation techniques are proposed.

High-speed circuit radiation within an enclosure leads to cavity resonance that can have critical impact on other electronic components housed within the same enclosure. The amplified electric field in the enclosure can couple to critical circuits leading to either hard or soft failures. One measure to gauge the resonances of an enclosure is through the determination of S- parameters between certain ports connected to the enclosure. In time-domain based techniques, a direct calculation of S- parameters can be very costly in terms of execution time and computational space which is directly related to computer memory allocation. In this work, different numerical methods needed for efficient prediction of S-parameters are proposed and evaluated for their effectiveness and accuracy. Once an efficient procedure is established for calculating S-parameters, novel topological variations within the enclosure can be tested before manufacturing using accurate numerical prototyping. The proposed numerical S- parameter calculation algorithms are validated by comparison to laboratory measurements.

Mathew, Sony (M.S. Mechanical Engineering)

Remaining life assessment Methodology for electronic hardware under vibration and shock Loads

This thesis assesses the remaining life of an electronic hardware subjected to multiple random vibration profile loading and shock loading during its operation. It presents a case study of remaining life assessment of a 3 ampere combination switch circuit card from the integrated electronic assembly (IEA) of the space shuttle solid rocket booster (SRB).

The successor to the Space Shuttle, the second-generation Reusable Launch Vehicle (RLV), is not expected to be ready before 2020 and hence NASA hopes to extend the usage of the Space Shuttles into the year 2020. Previously NASA has observed some component failures in the IEA circuit cards such as failure of glass bodied diode and broken capacitor leads. NASA has asked its major contractors to conduct remaining life assessment of the key components of the Space Shuttle. A remaining life assessment will help in making an evaluation of the condition of the electronic hardware and in developing a plan for operation and maintenance.

Assessing the remaining life of an electronic hardware is the process of estimating the ability of the hardware to meet its required specifications while operating in its life cycle environment for the rest of its designed service life. The remaining life assessment is based on the damage accumulated, due to the life cycle loading conditions in the past, at the site on the printed circuit board that is most susceptible to failure. In previous studies conducted at the Computer Aided Life Cycle Engineering Electronics Products and Systems Center (CALCE EPSC) at the University of Maryland, the remaining life of electronic hardware has been conducted using a virtual assessment method. The previous studies have focused on the assessment of printed circuit cards subjected to thermal loading and single vibration profile loading conditions.

This case study hardware was subjected primarily to multiple repetitive shock and vibration. The thesis presents the methodology for conducting the remaining life assessment of electronic hardware subjected to multiple random vibration and shock loads. The remaining life assessment utilized virtual assessment and life test. The virtual assessment method focused on assessing the component to circuit card solder joint interconnects. The life cycle environment multiple random vibration load and shock load data was transformed to a form suitable for use in the virtual assessment. The life test random vibration and shock loads were developed from the actual life cycle environment loads.

Meyyappan, Karumbu Nathan (Ph.D. Mechanical Engineering)

Failure Prediction of Wire Bonds due to Flexure

Solid state power modules are subjected to harsh environmental and operational loads. Identifying the potential weak-links and dominant failure mechanisms associated with the application is very critical to designing such power modules. Failure of the wedge-bonded wires is one of the most easily identifiable causes of failures in power modules. Thermal cycling can induce the wires to flex in response to the load cycle. The heel of the wire is already weakened due to the ultrasonic bonding process and the flexing motion is enough to initiate the crack in the heel of the wire. Considering the magnitude of this failure mechanism in power modules, a very generalized first-order physics-of-failure based model has been developed to quantify these flexural/bending stresses. A variational calculus approach has been employed to determine the minimum energy wire profiles. The difference in curvatures corresponding to the wire profiles before and after thermal cycling provide the flexural stresses. The stresses/strains determined from the load transformation model is then used in a damage model to determine the cyclesto failure. The model has been validated against temperature cycling test results. Also, the effects of residual stresses (introduced during the loop formation) on the thermal cycling capability of these wires has been studied. It is believed that the ultrasonic wirebonding process renders the wires weaker at the heel. Efforts have been made to simulate the wirebonding mechanism using Finite Element Analysis. The key parameters that influence the wirebonding process are identified. Flexural stresses are determined for various wire profiles that correspond to different bond forces.

Additional design constraints may prevent some of the wedge-bonded wires from being aligned parallel to the bond pads. The influence of having the bond pads with a non-zero width offset has been studied through finite element simulations. The 3D minimum energy wire profiles used in the modeling has been obtained through a new energy minimization based model.

Rogers, Keith (Ph.D. Mechanical Engineering)

An Analytical and Experimental Investigation of Filament Formation in Glass/Epoxy Composites

The drive to increased circuit density with smaller printed wiring board (PWB) geometries and increased layer counts in multi-layer boards along with the increased use of electronics in harsh environments for high reliability and safety critical applications (automotive, avionics, medical, military) have made short circuiting of PWBs due to growth of conductive filaments between biased conductors a major concern. In addition, the impending implementation of lead-free soldering processing, which may affect laminate stability and materials choices, can increase the potential for conductive filament formation (CFF) failures will also continue to increase. To prevent these types of catastrophic failures, it is necessary to understand the roles and synergistic effects of environmental conditions, material properties and manufacturing quality in accelerating or deterring CFF.

In this dissertation, four laminate types (including a halogen free) and three conductor spacings were tested at different voltages in accordance with IPC TM-650, allowing a ranking of these laminate types based on resistance to CFF. Demonstrated is the use of an innovative technique, the scanning quantum interference device, to verify and locate the internal short circuits based on magnetic images fields generated by current paths. With this technique, a new variant of filament formation in glass/epoxy composites: vertical filament formation (VFF) was identified. The conductive filaments found at failure sites in plated through hole-to-plated through hole and also plated through hole -to-copper plane were observed from cross-sectioning techniques, verifying that the failures were indeed due to CFF. A test standard to identify hollow glass fibers, a potential path for filament formation in laminated PWBs was also created. It was also observed that board types, which show the longest time to failure due to CFF in PTH-PTH configuration, might not necessarily offer the best protection for PTH-plane geometry.

Based on insulation resistance measurements during the accelerated testing, it was seen that the IPC-TM-650 test specification of monitoring every 24 hours could allow intermittent failures to go undetected. The in-series 1 mega ohm resistor as specified by IPC-TM-650 may not be sufficient to prevent "blow-out" of some of the fragile filaments as seen in the intermittent nature of some of the insulation resistance drops. It was demonstrated that dielectric breakdown voltage values after exposure of the test boards to 85 C, 85% RH for 96 hours followed the same trend as the time to failure observed for the PTH-PTH failure data, suggesting that dielectric breakdown voltage can be an indicator to CFF susceptibility. This can save considerable time and cost due to the duration of the tests to generate failure and time in locating the failure sites to verify CFF, and the cost of the necessary testing equipment.

Singh, Pameet (Ph.D. Mechanical Engineering)

Forecasting Technology Insertion Concurrent with Design Refresh Planning for COTS-Based Obsolescence Sensitive Sustainment-Dominated Systems

There are many types of products and systems that have lifecycles longer than their constituent parts (specifically COTS - Commercial Off The Shelf parts). These lifecycle mismatches often result in high sustainment* costs for long field life systems (e.g., avionics, military systems, etc.) due to part obsolescence problems. While there are a number of ways to mitigate obsolescence, e.g., lifetime buys, aftermarket sources, etc., ultimately systems are redesigned one or more times during their lives to update functionality and manage obsolescence. Unfortunately, redesign of sustainment-dominated systems like those mentioned above often entails very large non-recurring engineering and system re-qualification costs.

Ideally, a methodology that determines the best dates for design refreshes, and the optimum mixture of actions to take at those design refreshes is needed. The goal of refresh planning is to determine:

To address the refresh planning goals above, a methodology called MOCA (Mitigation of Obsolescence Cost Analysis) has been developed. MOCA determines the electronic part obsolescence impact on lifecycle sustainment costs for long field life electronic systems based on future production projections, maintenance requirements and part obsolescence forecasts. The methodology determines the optimal design refresh plan to be implemented during the system¡¯s lifetime in order to minimize the system¡¯s lifecycle cost.

For technology insertion decision making, MOCA uses a Monte Carlo/multi-criteria decision making hybrid computational technique in which a Monte Carlo is used to accommodate input uncertainties and Bayesian networks are used to make part upgrade decisions at design refreshes.

A case study is performed to demonstrate MOCA¡¯s capabilities on a NDU (Navigation Data Unit) that resides on a US Navy class of ships known as the LPD-17.

*Sustainment in this context means all activities necessary to: keep an existing system operational, and continue to manufacture and field versions of the system that satisfy the original and evolving requirements.

Zhang, Qian (Ph.D. Mechanical Engineering)

Isothermal Mechanical and Thermo-Mechancial Durability Characterizaton of Selected Pb-free Solders

As major mechanical, thermal, and electrical interconnects between the component and the PWB, solder joints are crucial for the reliability of the most electronic packages. Due to the hazards of Pb in the environment and its effect on humans and marketing competition from Japanese manufacturers, the conversion to Pb-free solders in the electronics industry appears imminent. There is an urgent need for constitutive properties, mechanical durability and thermo-mechanical durability of Pb-free solders.

A partitioned constitutive model consisting of elastic, plastic, primary creep and secondary creep models is obtained for the Sn3.9Ag0.6Cu solder and the baseline Sn37Pb solder from monotonic and creep tests conducted on Thermo-Mechanical-Microscale (TMM) setup. The comparison between two solders shows that Sn3.9Ag0.6Cu has much better creep resistance than Sn37Pb at the low and medium stresses.

The isothermal mechanical durability of three NEMI recommended Pb-free solders, Sn3.9Ag0.6Cu, Sn3.5Ag, Sn0.7Cu, is tested on the TMM setup under low and high creep test conditions. The damage propagation rate is also analyzed from the test data. The generic Energy-Partitioning (E-P) durability model is obtained for three Pb-free solders by using the incremental analytic model developed for TMM tests. The scatter of the test results from the prediction by these E-P durability model constants is small.

The thermo-mechanical durability of the Pb-free Sn3.8Ag0.7Cu solder is investigated by a systematic approach combining comprehensive thermal cycling tests and finite element modeling. The effects of mixed solder systems, device types, and underfill are addressed in the tests. Thermal cycling results show that Sn3.8Ag0.7Cu marginally outperforms SnPb for four different components under the studied test condition. The extensive three-dimensional viscoplastic FE stress and damage analysis is conducted for five different thermal cycling tests of both Sn3.8Ag0.7Cu and Sn37Pb solders. Power law thermo-mechanical durability models of both Sn3.8Ag0.7Cu and Sn3Pb are obtained from thermal cycling test data and stress and damage analysis. The energy-partitioning durability models of two solders are also obtained. It is found that the slopes of the plastic and creep curves in the E-P damage model of Pb-free solders for thermal cycling are steeper than those for mechanical cycling and those of Sn37Pb solders.