Created: 03/09/01

CALCE EPSC Graduate Student Theses (2001)

Ardebili, Halen (Ph.D. Mechanical Engineering)

Moisture Diffusion and Reliability Issues Associated with Moisture in Plastic Encapsulated Microelectronics

Plastic molding compounds have become the leading encapsulating materials in today's microelectronic packaging industry. Plastic encapsulated microelectronics (PEMs) offer several advantages over hermetically sealed packages. Lower design and manufacturing costs, lighter weight, smaller size, higher productivity, and improved part reliability are some of the advantages of the plastic encapsulation over its hermetic counterpart [Tummala] [Pecht] [Harper]. Plastic molding compounds, however, are hydrophilic and absorb moisture when exposed to humid environment.

Plastic encapsulated devices can be subjected to humid environment throughout their life cycle from manufacturing to storage to operation stage. Packaged IC devices may be subjected to humidity levels up to 60% relative humidity (RH) and temperature levels up to 40oC during operation and storage. The electronic devices operating at outdoor ambient environment can be subjected to humidity levels up to 100%RH and temperatures exceeding 50oC. As will be discussed in more details later on, moisture can adversely affect reliability of plastic encapsulated microelectronics (PEMs). Moisture in PEMs can lead to many deleterious effects like cracking, delamination, and metallization corrosion.

Various measures have been taken to prevent moisture from getting to the package or to the integrated circuit (IC) device. The prevention methods such as dry bag sealing, over-mold-coating of the PEM package, passivation of the IC chip, and conformal coating are often effective in only slowing down moisture ingress to the package or to the IC chip. The prevention methods are prone to failure and can eventually allow moisture vto reach the package and the IC chip. Also, not all packages are subjected to strict moisture prevention measures. More accurate experimental and theoretical moisture diffusion studies can lead to more accurate and effective prevention methods.

Many studies have addressed and modeled moisture diffusion in plastic molding compounds and plastic encapsulated microelectronics (PEMs) [Crank] [Shook] [Wong,1998] [McLaren] [Galloway] [Tencer] [Taylor] [Belton]. Many studies have investigated the deleterious effects of moisture on the electronic package [Adachi] [Wong,1998] [Fan] [Galloway] [Taylor] or plastic molding compound [Morgan] [ElSaad] and proposed models that predict moisture effects on material properties. As will be discussed more extensively later in Chapter 2 of this thesis, moisture diffusion is not a simple phenomenon and there are many factors and variables that affect it. Due to the importance and the complexity of this subject matter, further studies are needed.

Broadwater, Keita (Ph.D. Mechanical Engineering)

Characterization and Health Monitoring of Epoxy-Cured Fiber Optic Connectors Via Fiber Optic Sensing

Optical Fiber Connectors are passive components used to link two fiber links or a fiber link to a photonic device. One widely used type of fiber connector, a design that uses a thermally cured epoxy adhesive, has been evaluated via strain sensors. Strain sensors were used to evaluate the strain incurred by the optical fiber as a result of installation and subsequent environmental testing. Discussed will be preliminary mechanical modeling, and a strain analysis using Bragg grating (BG) based strain sensors. Since the stain sensors were not exposed to uniaxial loading, mechanical modeling was used to determine the optimum placement of the sensors and the expected response. Also discussed are ongoing studies to evaluate the viscoelastic behavior of the epoxy and its effect on the strain state of the connector assembly.

Many fiber optic components utilize a thermally cured, epoxy resin as an adhesive. The properties of this solidified epoxy, determined typically by composition and cure schedule, are frequently evaluated experimentally by differential scanning calorimetry (DSC) and thermomechanical analysis (TMA). A disadvantage of these techniques is that they measure the properties of bulk samples. In practice, the epoxy is typically in a thin-film form. The properties of a thin film are not necessarily the properties of a bulk sample. A technique is presented that measures the glass transition temperature (Tg ) in fibers encapsulated in zirconium ferrules by use of an in-situ strain sensor, a Bragg grating. This technique has the advantage that it can determine the Tg of the epoxy in the environment and geometry of use. Using this technique will allow a manufacturer or end user to qualify a product based on direct measurements of the product itself and not information supplied by a vendor or bulk sample measurements, which may not be accurate for a specific application. Since fibers adhered in ferrules are used in a variety of optoelectronic products, this technique has broad-ranging applications.

Bardhan, Samuel (M.S. Mechanical Engineering)

Electronics Technology Insertion into Low Volume Complex Electronic Systems (LVCES)

The LVCES industries such as defense and avionics have transcended from a position of dictating terms with mil-spec part suppliers to a current situation where mil-spec part availability has declined and part manufacturers are no longer interested in manufacturing low volume mil-spec parts. The LVCES industry therefore has a restricted supply chain that does not promise LVCES specific (Ex. Mil-spec) parts beyond 2005. Decreasing availability of mil-spec parts has resulted in LVCES industry system designers leaning towards the use of commercial electronics in LVCES industry systems. LVCES are planned to have very long service lives, be repairable and operate under harsh environmental conditions. This raises reliability challenges of using commercial grade electronics.

The thesis is written to address a wide audience including engineers and managers interested in understanding the risks inherent in the LVCES industries and shaping strategies for mitigating those risks while conducting technology insertion. It aims to help manufacturers of low volume products to plan technology insertion for their systems by providing information on the technology trends that are likely to affect future LVCES designs, a methodology to conduct technology insertion, and guidelines to analyze and mitigate the risks of technology insertion. Members of product teams, marketing professionals, business development professionals, contract negotiators, proposal writers, and designer's will also find the guidance provided in this thesis particularly useful. It will be useful for all personnel who are instrumental in facilitating relationship building with suppliers and customers. It is also a guide to understand the nature of the LVCES environment.

Low volume is defined as the total number of electronic systems that are built in a year or as part of a contract. Quantification* of low volume is given below through the following example.


Complexity of an electronic system, is defined as the design and verification difficulty arising out of the number of parts, the number of part types used in a system, the number of interconnections required in a system, f is the number of functions the system has to perform, and K is a convenience constant. Complexity also includes the difficulty to predict the behavior of a system from knowledge of the individual circuits studied in isolation from one another and the level of effort required for verification.
Electronic: The term "electronic" is restricted to equipment constructed from electronic components.
Systems: A system is one or more electronic units which, when connected together, perform one or more functions in the end application.

Ciocci, Richard (Ph.D. Mechanical Engineering)

Assessing the Migration to Lead-free Electronic Products

The electronics industry is facing a fundamental change to long-standing soldering processes as the switch to lead-free solder is imminent. Pending legislation, which calls for a ban on lead in electronics, may be the reason that attention on lead-free technologies has escalated, but recognition that lead-free solder is a product differentiator may be the cause for action. Lead- free solder has been used successfully, but there are processing and reliability issues, which must be overcome. However, a close look at the impending industry-wide change to lead-free solder shows that companies are already using alternative materials and are already marketing products to environmentally- aware consumers.

The debate will continue over whether lead in electronics should be banned as it represents a small amount of the material that is used for consumer products. Expecting the switch to lead free to be inevitable, this research answered various questions facing manufacturers and suggests steps manufacturers can take to prepare for the change. Technical, legislative, market, economic, supply chain, and environmental issues regarding the migration to lead-free solder are included.

Davuluri, Pavan (M.S. Mechanical Engineering)

A multi- scale modeling approach for stress analysis of electronic interconnects

This dissertation introduces the concept of multi-scale modeling for studying the structural response of microelectronic devices, in order to facilitate efficient simulation methodologies to be incorporated in the development phases of electronic products with complex interconnects. This methodology is faster than two-step global-local analysis using finite elements or alternative stress analysis techniques such as the multi-domain Rayleigh Ritz (MDRR) and Nested Finite Element Method (NFEM) and is based on a single step global-local approach.

Failure occurs in most electronic assemblies at a localized critical region under the influence of one or more damage mechanisms. Hence from an analysis perspective, it is necessary to accurately represent the electronic assembly in that region while the remaining non-critical regions of the electronic package may be modeled in a more simplistic manner, as long as they closely capture the load path in the non-critical region. This thesis uses the above premise to represent non-critical regions of a package with an elastic compact mechanical model and an NFEM-based model to represent the critical region of interest. The compact mechanical model, uses first-order shear deformable shell elements as structural equivalents of the package and printed wiring board (PWB) and first-order shear deformable beam elements for the electronic interconnects. A Material Dependent Shear Deformable Theory (MDSDT), developed at CALCE, was used to find equivalent properties for the elements used in the compact mechanical model. This technique was validated by comparing displacement fields with those obtained from moir analysis for a CSP assembly.

In order to represent the coupling between the critical region modeled with NFEM and the rest the non-critical assembly, the compact mechanical model is interfaced with the NFEM model using multi-point constraints. In contrast to traditional global-local techniques that involve a two-step analysis, here, the compact model and NFEM are integrated in a single effective structure. Most techniques use the global model to provide boundary conditions for the subsequent local analysis. This thesis, however, assembles the stiffness matrices from the two structures and applies boundary conditions and multi-point constraints to the single matrix. This approach was implemented for elastic and elastic-plastic analysis of the critical region. Results were found to be in reasonable agreement with those from a similar representation in commercial finite element software.

Gopinath, Deepak (M.S. Mechanical Engineering)

Multi-Objective Placement Optimization of Power Electronic Modules on Liquid Cooled Heat Sinks

The widespread use of power semiconductors has given rise to a host of thermal design issues. The integration of various power devices into a single programmable block as envisioned by the Navy^s Power Electronic Building Block program (PEBB) is projected to significantly increase heat dissipation rates up to 2-3W/mm2. Thermal design and characterization of power electronic packages consequently have to be prepared to meet these challenges as they arise. Choosing the right FLC heat sink and determining optimal power module placement is an important issue for packaging engineers. The present study develops a methodology for optimum power device placement and preliminary cold plate sizing. Rapid thermal calculation models or compact thermal models within a genetic algorithm based multi-objective optimization framework are the basis of the methodology. The methodology is demonstrated for the optimal placement of multiple power modules on liquid cooled heat sinks. A reduced thermal model to solve the placement problem, including compact models for PEBB devices and liquid cooled heat sinks was developed and integrated within the optimization framework. The effectiveness of this methodology as a preliminary scouting tool to perform tradeoff analysis for heat sink sizing and optimal component placement is demonstrated through few, selected case studies.

Goray, Kunal (M.S. Mechanical Engineering)

Durability of Surface mount components under flexural loads

The study investigates the durability of interconnects for three different surface mount components under static twist loads. The components under study are two BGAs namely a LFBGA180 (low profile fine pitch ball grid array) and a TFBGA81 (thin fine pitch ball grid array) and two leadless Metal Lead Frame (MLF) components of 32 and 40 I/O. A twist test setup is built which can apply controlled twist loads on the test board. The life cycle loads at the board level are determined experimentally using the test set up. The components are mounted on a FR4 substrate and subjected to displacement based twist loads. The overstress twist load limit is determined and the test specimen is characterized by mounting rosette strain gages on the PWB under each component. An accelerated test load profile is developed. Accelerated life test is carried out for the components and the cycles to failure at each load level is recorded. The accelerated test is simulated using a global-local finite element modeling technique, for the BGAs. The solder strain in the critical interconnect is determined at each load level by averaging the solder strain around the critical region over 8% solder volume. Hysteresis plots are generated for the solder interconnects after the plastic energy in the identified critical regions has stabilized.. A modified Coffin-Manson strain-range fatigue model is used to estimate the durability under the test loads. The finite element models are then loaded with the life cycle loads and the acceleration factors are determined for the life cycle loads. Using the test data and the acceleration factors, the durability is estimated for life cycle loads. The leadless MLF component is not modeled but only tested. Based on the test results the MLF is the most durable surface mount package for twist loads with the MLF outlasting the BGAs by almost 40 times. Since finite element simulations are not performed for the MLF the fatigue test results are plotted against the PWB shear strain under the component to show the relative disabilities of the compoenents.

Haswell, Peter L. (Ph.D. Mechanical Engineering)

Durability Assessment and Microstructural Observations of Selected Solder Alloys

The continuous miniaturization of electronic packages and systems combined with ever-decreasing product development cycles requires continuous refinement of the analytical and numerical models that are used as design tools and to predict the durability of products subjected to field or laboratory conditions. As the interconnect length scales approach the alloy microstructural feature sizes, the need to incorporate such small-scale parameters becomes more urgent. Likewise, shorter product development cycles combined with downward cost pressure necessarily restricts the time and resources available for carrying out experimental verification of product durability, consequently increasing the reliance on simulations for design validation. Solder interconnects have traditionally been and continue to be a weak link in most conventional electronic packages, so a more complete understanding of these materials is highly desirable. Furthermore, alternative interconnect materials, including those for high-temperature, lead-free and multi-stage processing applications, have only recently been studied and have been subjected to only the most basic characterization studies.

In this dissertation, the durability of two solder interconnect alloys, the standard Sn63Pb37 eutectic and an important lead-free alloy, is investigated using a combination of experimental and analytical techniques. A miniature, solid state, mechanical testing system is developed to provide a means for the testing in shear of solder alloy specimens with length scales similar to those seen in typical interconnects. Cyclic, durability tests are conducted over suitable ranges of amplitude, deformation rate and temperature using multiple test control algorithms; monotonic and load- controlled tests are also conducted at different temperatures and load levels. Macro-scale constitutive and durability behavior of the solder alloy can be observed and modeled directly from the basic experimental data (i.e. load and displacement histories). Localized behavior of the test solder joints is inferred from numerical analysis of the test structures and conditions. In addition, several test durability test approaches and methodologies are evaluated. The effects of using different test control algorithms on durability modeling, consequences due to choice of failure definition, and the effect of accounting for the complete cyclic load history instead of traditional initial cycle metrics are examined.

Kalchuri, Shantanu (M.S. Mechanical Engineering)

Effects of Low Temperature Power Cycling on Reliability of Power Electronic Devices

Commercial power electronic devices often dissipate large amounts of power, which can cause the temperature of the device to rise rapidly when the device is switched on and fall rapidly when the device is turned off. These rapid changes in temperature upon repeated power on / off cycling can cause serious reliability concerns. This is thought to be especially true for power electronic devices required to start and operate at temperatures well below freezing, in the range of -55oC and -65oC, in applications like airplanes at high altitudes, submarines in regions like North Pole and Antarctica. At low temperatures, elastic modulus of die attaches increases, which can generate high stresses in the die and the die attach. This can lead to die attach degradation and in extreme cases die cracking. The aim of this study was to quantify the effects of low temperature power cycling on the reliability of power electronic devices. Four different commercial plastic encapsulated component types were power cycled at temperatures of -55oC and -65oC. Electrical and thermal parameters were monitored at intervals during the test to gain insight into the package degradation. Non-destructive failure analysis was also done at intervals during the test to look for delamination and cracking in the packages, and degradation of the die attach, which was singled out as the primary reliability concern. Destructive failure analysis was performed after the cycling to visualize the nature of degradation. It was found that the ambient temperature does not have a significant effect on the amount of degradation within the temperature range studied. Finite Element Analysis was done to understand the physics behind the failure. The high peeling stresses at the edge of the die attach were determined to be the root cause of failure.

Liu, Weifeng (Ph.D. Mechanical Engineering)

Reliability Assessment of IC Component Sockets

An IC component socket is an electromechanical system that provides a separable connection between an electronic component and a printed circuit board. IC component sockets have found extensive applications in the microelectronics industry because they offer many advantages to IC design and to component test, assembly, upgrade, repair and supply chain management. However, IC component sockets introduce some failure opportunities and bring about reliability concerns. To address the reliability concerns of IC component sockets, manufacturers perform qualification testing. However, there are some concerns that these "traditional" qualification methods do not address some of the unique failure mechanisms of today's high I/O elastomer sockets.

This thesis provides an investigation of the failure mechanisms of a commercial metal particle-in-elastomer socket and aims to discover if new failure mechanisms exist, the principles of these mechanisms and how the qualification methods could be improved. This investigation takes into account the functional, performance and life cycle requirements, the environmental and operational conditions, the material and design properties, and the potential failure modes and mechanisms. The critical socket design and material properties were examined through characterizing a single interconnect. Through this characterization, the limits of operating parameters were defined, and potential risk areas and failure mechanisms of the elastomer interconnects were revealed; among them, stress relaxation, radial deformation, electrical instability under thermal and mechanical impacts, silver reaction with chloride and sulfur, elastomer-silver particle dewetting, and elastomer stiction to contact pads were found to be the most serious concerns, as they may lead to contact open, contact short, or intermittent failures, and raise the reworkability concern as well. Issues such as loading control mechanisms, panel non-coplanarity, socket manufacture and component assembly quality were also discussed as they may contribute to socket failures. Finally a list of accelerated stress tests as well as test configuration and guidelines were provided to address these failure concerns of the elastomer sockets under the specified life cycle conditions.

Majeed, Majed (M.S. Mechanical Engineering)

Multifunctional Dual-Stiffness Sensor for Insitu Real-time Stiffness and Energy-Density

In this study, a new mechanical sensor system is proposed for smart health monitoring. Two strain sensors of different stiffnesses are integrated into a host structure. Since the strain measured by the two sensors depends on their stiffnesses as well as on the stiffness of the surrounding" host material, then by the use of an inverse problem one can recover the local stress and strain histories in the host. Thus, it is possible to deduce the local stress and strain histories stiffness and strian energy desity. Since the sensors are embedded in a structure that is subjected to a comples three dimensional stress state, Eshlby's equivalent inclusion method is used to derive the elastic fields inside the sensors. A complete analytical derivation is presented for one dimensional and two dimensional loading. The sensitivity of the new system of dual-stiffness sensors is parametricall investigated by varying the stiffnesses of the host, the sensor stiffness and sensor geometry. Error propagation for the different input parameters, considering both the one dimensional and two dimensional cases, is analyzed for embedded sensors subjected to multiaxial stress state. Proof of concept by experimental and finite element verification is conducted by means of simple uniaxial tests for different hosts of varying stiffnesses with two surface-mounted sensors. A third sensor was mounted on the specimens to verify the applied far field load. In addition, a numerical verification with finite Element Analysis (F.E.A) is presented. Results indicated that the concept is viable. The accuracy and sensitivity are excellent for compliant hosts, but decreases progressively for stiff hosts. This type of sensor is therefore ideal for monitoring health degradation either due to distributed homogeneous damage such as matrix microcracking in polymer-matrix composites or due to large deformations and crack propagation in the vicinity of the sensor in composite structures. When combined with appropriate damage model, this sensor technology will be a key enables for structural health monitoring.

Murray, Steve (M.S. Mechanical Engineering)

Aging and Qualification of Polyimide Dielectric Film

A common failure mechanism of polyimide dielectric is deadhesion by aging-assisted fatigue. Fatigue crack growth results from thermo-mechanical and hygroscopic stresses induced by changes in the temperature and humidity of the local environment, as well as by any mechanically applied loading such as bending or vibration. Environmental aging results from the simultaneous processes of hydrolysis and thermo-oxidative degradation, which are rate-determined by the average level of temperature and humidity of the local environment. Aging results in decreased strength and embrittlement of polyimide, and increases the crack growth rate under fatigue loading. Many adhesives that are sometimes used with polyimide dielectric when making multi-layer structures are also susceptible to fatigue damage and environmental aging. Deadhesion failure of products containing adhesives can occur by the propagation of a fatigue crack through either the polyimide or adhesive layers.

In order to design accelerated tests for deadhesion, a model is needed that quantifies environmental aging and explains how it can be accelerated. A methodology to characterize the rate of aging as a function of temperature and humidity using peel and tensile tests is proposed, and empirical models for the aging of Kapton E polyimide film with titanium barrier metallization, unmetallized Kapton E polyimide film, and a siloxane-polyimide-epoxy adhesive on copper metallization are developed. These aging models can be used in combination with time-compression of fatigue loading cycles to design accelerated tests to evaluate the resistance to deadhesion of products containing polyimide dielectric and/or adhesive. An accelerated test plan for a multi-chip module used in a naval environment is presented to illustrate the methodology.

Radhakrishnan, Jagadeesh (M.S. Mechanical Engineering)

A Process-Based Cost of Ownership Mod el for Inclusion of High-Frequency Micromachined Structures in a Conventional

Micromachining refers to the technologies and practice of making three-dimensional structures and devices with dimensions on the order of micrometers. One of the goals of Micromachining is to integrate microelectronic circuitry with micromachined structures, to produce completely integrated systems called microsystems. Such systems are envisioned to have the same advantages of low cost, high reliability and small size as silicon chips produced in the microelectronics industry. The field of MicroElectroMechanicalSystems (MEMS), which refers to micromachining of silicon wafers, has been enabled by massive parallel fabrication methods in the semiconductor industry. But the economy of scaleand other economic models governing the semiconductor industry are transposed too often without sufficient differentiation to make rational predictions about the market for MEMS-based products. The roadblocks to the realization of all the great things that MEMS can do include the issues of manufacturability, process compatibility and reliability. The key measure of these issues is cost. So, it is necessary to perform a detailed cost analysis for MEMS foundry.

This work develops a process-based Cost Of Ownership Model for the inclusion of high frequency micromachined structures in conventional IC. A sensitivity analysis is performed to study the impact of die size, wafer size, and number of micromachined structures per die on the various cost parameters. It was observed that a 12-inch diameter silicon wafers offers the best choice in terms of cost of addition of micromachined structure per die and in terms of effective wafer surface area utilization. The standards in the semiconductor industry today is an 8-inch diameter wafer; however, the next few years will be crucial to a transition to 12-inch diameter wafer which will result in a 30-40% die cost reduction.

Ragan, Daniel (M.S. Mechanical Engineering)

Detail Cost Modeling for use with Hardware/Software Co-Design of a System on a Chip

The interdependency of hardware and software leads to trade-offs in the optimum partitioning of functionality between hardware and software in the implementation of a system. While hardware and software have typically been described and designed using different formalisms, languages, and tools; hardware/software co-design attempts to integrate the respective design techniques with the goal of utilizing a single design methodology in the system design process. Despite the advantages predicated form the utilization of co-design methodologies, co-design tools are not yet an integral part of most design process and generally focus only on the prediction of system performance or co-verification of system functionality. This study extends the conventional focus of hardware/software co-design through the development of a new methodology and software toll that evaluates system development, fabrication, andtesting costs concurrent with hardware/software partitioning in a co-design environment.

This study utilizes a commercial co-design platform to analyze a virtual prototype of mixed hardware/software system. A digital camera, considered a good representation of mixed system, is modeled using functional and architectural block diagrams and system performance is simulated. Based on the determination of key metrics such as gate count and lines of software code, a second software tool called Ghost developed at the University of Maryland, evaluates software and hardware development, fabrication and testing costs. Using the co-design environment in conjunction with the Ghost tool allows the concurrent evaluation of effects of hardware/software partitioning choices on cost and performance.

The detailed case study of the digital camera's JPEG encoder chip reveals that production characteristics such as production quantity, level of reuse, and hardware/software partitioning have an effect on the optimal design under cost and performance standards. The influence of recurring and non-recurring costs is also demonstrated. In addition, Monte Carlo analysis is performed model uncertainty.

Raghavan, Ravi (M.S. Mechanical Engineering)

Analysis of Test/Diagnosis/Rework Operation Placement in the Technical Cost Modeling of Advanced Electrical Power System Modules

To remain competitive in the electronics industry, designers search for opportunities to control and reduce the system manufacturing costs. Of the manufacturing costs, the functional test and the rework costs can be very important drivers that significantly affect the total cost of manufacturing for many products. Modeling the cost of test/diagnosis/rework operations accurately and identifying the number and location of their placement in an assembly process often determines the extent to which the system designer can control and reduce the manufacturing cost. In this thesis, the focus of study is the cost-effective placement of test/diagnosis/rework operations in the Advanced Electrical Power System (AEPS) module assembly. By carefully reviewing the cost tradeoffs that are characteristic of the number and location of these placements, the ultimate goal is to reduce manufacturing costs. The concept of Test Economics Phase Diagrams is introduced and promoted as a tool for the evaluation and comparison of tradeoffs that are obtained for various combinations of the test/diagnosis/rework placements and various properties used to characterize the test, diagnosis, and rework operations.

The process placement research in this thesis is enabled by the development of a test/diagnosis/rework cost model that is more detailed than previously developed models. An analysis of the model is performed to study the effect of various process variables on the cost, including fault coverage, false positive fraction, variably number of rework attempts, diagnosis and rework success rates, and yields modeling the introduction of defects throughout the test/diagnosis/rework process.

The test/diagnosis/rework cost model and results presented in this study can be used by the designer to obtain and analyze important decision-level data for evaluating various tradeoffs involving cost and yield in an electronic system assembly process. This information could be ultimately used in reducing manufacturing and maintenance costs, resulting in higher quality systems at lower cost.

Ramakrishnan, Arun (M.S. Mechanical Engineering)

Healthand Life Consumption Monitoring Using Sensor Technologies

Electronic system failure is influenced by several parameters, such as temperature, humidity, vibration, pressure, and radiation, either acting independently or in various combinations, intensities, rates of change, and durations. With the exception of infant mortality failures, a number of systems have been observed to fail over time by gradual accumulation of damage due to operation in their life cycle environment. Hence, monitoring of the life cycle environment lends itself to a scheme for estimating the damage in a system, which can be used as a metric of when the system may be expected to fail. A well-designed maintenance scheme based on a health and life consumption monitoring methodology can then be used as a method to predict and prevent system failure and to reduce maintenance costs. This thesis describes the development of a physics-of-failure-based methodology for determining the life consumption in a system. The various steps involved in life consumption monitoring, including monitoring the life cycle environment, data simplification, reliability analysis, and damage assessment have been documented. Algorithms for converting raw field data recorded by sensors to a form compatible with the input requirements of physics- of-failure models while preserving the necessary characteristics for damage calculation have been developed and documented. Methods for storing, transmitting, and retrieving the data collected by sensing equipment for subsequent analysis have also been described.

In order to demonstrate the use of the methodology, a self-powered environmental data recorder has been procured and used to record the temperature and vibration loads on a printed circuit board placed under the hood of a car. The data collected has been applied to a specific failure mechanism (solder joint fatigue) using the calcePWA analysis software, and the life consumption in the board due to temperature and vibration loading has been calculated. The calculated remaining life has then been compared with temperature cycling test results on the board.

Sahasrabudhe, Shubhada (M.S. Mechanical Engineering)

Implementation and interpretation of Failure Free Operating Periods and Associated Confidence Limits in Electronic Systems Using 3-Parameter Weibull Distribution

The most common specification related to electronic system reliability is Mean Time Between Failures (MTBF) or Mean Cycles Between Failures (MCBF). MTBF reliability prediction methodology is usually based on an exponential distribution that assumes a constant failure-rate, implying that random failures and faults are inevitable.

A Failure Free Operating Period (FFOP) is defined as a period of time (or appropriate units) during which no failures, resulting in a loss of system functionality occur. The FFOP approach is anticipatory by nature, i.e., it is based on the identification and control of the causes of unreliability with the aim of improving equipment reliability in service. In this study, a 3-parameter Weibull distribution is used to represent the part failure distribution when modeling FFOP. By varying the parameters, the 3-parameter Weibull distribution can be reduced to many other distributions such as the Exponential, Raleigh, and Lognormal. Using the Weibull failure distribution makes it possible to determine decreasing, constant or increasing failure rates depending on the failure data.

This thesis presents a mathematical model for the estimating the FFOP and associated confidence limits at a chosen confidence level for:

The methodology developed in this thesis has been shown to successfully estimate FFOP and associated confidence limits at any confidence level for a single unit as well as multiple units in series and active redundant configurations. The methodology was verified for the single unit case by comparing the point estimate and the interval estimate values of FFOP obtained from the methodology developed in this thesis with those computed using Maximum Likelihood Estimation Method (MLE).

MLE assumes a normal distribution of the FFOP for the confidence interval estimation. The calculations based on this normality are appropriate for small sample sizes; they become exact as the sample size increases. Since typical sample sizes employed for physical reliability testing are of the order of 10, confidence limits calculated using MLE might have an associated error. The model developed in this thesis does not, a priori, assume any distribution on FFOP but predicts it. For sample sizes of the order of 10,000, the FFOP and confidence limit estimation by the methodology developed in this thesis and by MLE agree within 0.5%.

The model has been implemented in the calcePWA software tool as part of an overall virtual qualification strategy and has been applied to selected parts on Honeywell's AS900 FADEC CPU board. The unit-level and system-level FFOP analysis was performed on these parts and the behavior of the system-level FFOP compared to the behavior of its constituent unit-level FFOPs was studied.

Sangalli, Nicoletta (Ph.D. Mechanical Engineering)

Development of Crack Propagation Models for Soulder Joints under Creep-Fatigue Conditions

In electronic assemblies, solder joints are the mechanical and electrical connections between the components and the printed wiring board. In the design phase or in the failure analysis of an electronic assembly, it is crucial to estimate the solder joint life of an electronic component under certain load conditions. Specific damage models are applied to predict solder joint life based on the failure mechanism that caused the failure. In temperature cycling, the failure mechanism for the solder joint is creep-fatigue. In this thesis, two different kinds of components are analyzed to predict the solder joint life: the leadless chip resistors/capacitors and the sluggers. A fracture mechanics crack propagation damage model is proposed for eutectic solder Sn63Pb37 under creep-fatigue conditions, and other empirical crack propagation models are investigated. The fracture mechanics damage model developed is a relationship between C* and the crack growth rate, and it is based on experiment data. It turns out that a power law relationship relates C* and crack growth rate. C* can be used only in steady state creep conditions, and the energy rate definition given by Landes and Begley is used to calculate C*. The contribution of J is neglected in this model. The cyclic contribution is indirectly accounted into C* because it is calculated during cyclic loads instead of monotonic loads. This fracture mechanics damage model can be used to predict the solder joint life of electronic components once the creep steady state conditions are developed in the solder joints and once C* is determined from FEA modeling.

Temperature cycling experiments are applied on sets of leadless chip resistors, capacitors and sluggers to study the crack growth behaviour. Two or three components are periodically removed and cross-sectioned to measure the crack lengths. Darveaux's crack propagation model is applied to the slugger to verify if the model can be used for components different from those for which it was developed. Two other empirical crack propagation models are proposed based on the crack propagation behaviour in the solder joints of the leadless chip resistors and the sluggers. Finally, an initiation damage model is also evaluated to predict the solder joint life of leadless chip resistors and capacitors, and the simulation results are compared with the experiment results.

 

Sexton, Kontay V. (M.S. Mechanical Engineering)

Formulation of Simple Model to Assess Microvia Thermal Cycle Fatigue Life

In the profit driven world of consumer electronics, reliability is often an afterthought. With emphasis being placed mainly on time to market and performance in a sort of "smaller, better, faster" frame of thought, little time is left for rigorous analysis of reliability. Reliability, however, is a critical component that still commands a high degree of importance. After all, a design can be better than all the rest performance wise but if it does not survive it^s required design life, it is doomed to failure.

HDI (high density interconnect) technology, along with flexible circuits, has been described by some as the future of microelectronics. A large part of this technology relies a great deal on microvias as a interconnect solution.? Thus the goal of this work was to examine all of the factors which affect microvia reliability and to produce a tool that will take into account the most critical design factors in order to predict life.To accomplish this FEA (finite element analysis) modeling was 'used along with the technique of design of experiments (DOE).' In this way the physics of the structure's response to environmental loading was used to develop a simple life model.

Sidhu, Jaspreet (M.S. Mechanical Engineering)

Reliability Assessment of Thinpak Power Module for Thermal Cycling Environments

Solder joint failure is a major reliability concern in power module packaging because of the high operating temperatures involved in power device operation. These high temperatures combined with the thermal expansion mismatches in adjoining layers, cause buildup of shear and peeling stresses and inelastic strains in the solder material. These stresses and strains eventually cause cracking and delamination of the solder.

ThinPak is a power semiconductor packaging technology, which has shown promising electrical characteristics for its inclusion into the Navy/DOE Power Electronics Building Blocks (PEBB) program, which seeks a universal, fast switching, reliable and efficient power package capable of use in multiple applications. This thesis addresses the solder reliability issues in the ThinPak module from a virtual qualification standpoint. Strain and hysteresis energy based damage models are used for life prediction and the parameters required for these models are extracted from the stress analysis of a two-dimensional finite element analysis of the ThinPak. A hysteresis energy based crack propagation model is used to estimate the time for a complete crack to propagate in the most stressed eutectic solder layer and good correlations are drawn with experimental results.

Effective allocation of resources to product improvement requires a solid understanding of the relationship between manufacturing variability and product reliability. A 'virtual design-of-experiments' approach is used to estimate a simple relationship between the product life and material/dimensional parameters. A Monte Carlo simulation technique is used to study the effect of variability in the product attributes and thus a probabilistic life distribution is achieved.

Singh, Pameeth (M.S. Mechanical Engineering)

Design Refresh Planning Optimization Driven by Electronic Part Obsolescence

The rapid growth of the electronics industry has spurred dramatic changes in electronic parts. Increases in speed, reductions in feature size and supply voltage, and changes in interconnection and packaging technologies are becoming events that occur almost monthly. Consequently, many of the electronic parts that compose a product have life cycles that are significantly shorter than the life cycle of the product. This life cycle mismatch problem requires that during design, engineers be cognizant of which parts will be available and which parts may be obsolete during a product's life. This problem is especially prevalent in avionics and military systems, where systems may encounter obsolescence problems before being fielded and nearly always experience obsolescence problems during their field life. This problem is exacerbated by manufacturing that takes place over long periods of time, and the high cost of system re-qualification that makes the design refreshes extremely expensive.

Many part obsolescence mitigation strategies exist including: life time buy, last-time buy, part replacement, aftermarket source, uprating, emulation, re-engineering, salvage, and ultimately redesign of the system. Design refresh (or redesign) has the advantage of treating multiple existing and anticipated obsolescence problems concurrently and additionally allows for functional upgrades. Unfortunately, design refresh is also often a very expensive option, not just in non-recurring engineering costs, but also in potential system re-qualification costs. This thesis describes a methodology and it's implementation for determining the part obsolescence impact on life cycle sustainment costs for the long field life electronic systems based on future production projections, maintenance requirements and part obsolescence forecasts. Based on a detailed cost analysis model, the methodology determines the optimum design refresh plan during the field-support-life of the product. The design refresh plan consists of the number of design refresh activities, their respective calendar dates and content to minimize the life cycle sustainment cost of the product. The methodology supports user determined short- and long-term obsolescence mitigation approaches on a per part basis, variable look-ahead times associated with design refreshes, and allows for inputs to be specified as probability distributions that can vary with time. Outputs from this analysis are used as inputs to the PRICE Systems PRICE H/L commercial software tools for predicting life cycle costs of systems.

The methodology developed in this thesis has been applied to the Honeywell AS900 Full Authority Digital Electronic Controller (FADEC). The AS900 is a long field life (15-20 years), low volume (~ 3200 units), long manufacturing life (5-6 years), safety critical component used in engines for regional jets.

Swaminathan, Rajesh (M.S. Mechanical Engineering)

Experimental and Theoretical Methods for Estimating the Delamination of MEMS Chip-to-Chip Bonded Devices in a LIGA-Based Safety and Arming System

In the Integrated Circuit (IC) industry, the bond layer serves as the foundation and often the weak link in chip packages. Micro Electro Mechanical Systems (MEMS) packages are likely to have a greater number of bond layers with more stringent requirements than conventional ICs and assemblies. The additional bond layers arise from multiple interfaces inside and throughout the package. The bond layers in MEMS devices often must maintain precise component or chip alignment in order for the system to work properly. In addition, the bond layers may have to withstand long-term loading from both within the package and the macro-environment outside the package.

This thesis presents the bond requirements for a MEMS based Safety and Arming (S&A) device under development at the Naval Surface Warfare Center (NSWC) in Indian Head Maryland. The S&A system requires precise alignment between a micromachined silicon chip, a deflection delimiter, and a patterned Alumina ceramic chip or a silicon chip. Several candidate designs were subjected to a series of environmental and mechanical tests including thermal cycling, accelerated stress tests, mechanical shock, and die shear. A Scanning Acoustic Microscope (SAM) was utilized to measure initial delamination present in the bonded structures and to identify incremental damage due to environmental exposure. The tests were ultimately used to rank the suitability of the bond layer material for chip-to-chip attachment. Tested bond materials include epoxy, thermoplastic, and indium solder.

A Finite Element Modeling (FEM) approach was used to simulate the conditions the chip-to-chip bonded samples were exposed to during the die shear tests and to estimate the stresses experienced by the device. The FEM results are correlated with die shear measurements and the SAM-based delamination measurements.

Syrus, Toby (M.S. Mechanical Engineering)

Refinement of Part and Manufacturer Assessment and Update to Include Discrete Passive Parts

Parts selection and management is a process for evaluating the risks inherent in the use of an electronic part (e.g., resistor, diode, or integrated circuit), and then facilitate informed decisions regarding its selection and future management activities. One step in the process involves manufacturer and part assessment. These assessments are application-independent, hence they are not affected by the user's intended application. Manufacturer assessment is used to determine if the manufacturer's policies and procedures are consistent with producing quality and reliable parts, while part assessment evaluates the part's quality and integrity. These processes involve comparing data acquired for the manufacturer and part with predetermined criteria to determine their acceptability. This thesis presents the manufacturer and part assessment processes, the criteria developed for assessment, and their applicability to discrete passive parts. The process and criteria were developed by analyzing industry standards and existing company methods, consulting with industry and academia experts, and conducting a case study of 207 parts from 54 manufacturers, the results of which are provided. A method for assessing the return on investment of manufacturer and part assessment is also presented with an example.

Yoo, Dong-won (M.S. Mechanical Engineering)

Smart Thermal Management Systems Based on Solid Liquid Phase Change Materials (PCM)

Phase change materials (PCM) absorb energy as latent heat as they undergo a reversible phase transition from solid to liquid. The PCM thus acts as a thermal capacitor. By selecting materials that have appropriate melting temperatures and thermophysical properties, PCMs can be used for transient thermal management applications that involve stepwise, as well as periodic loads. In this study, a novel heat sink which uses PCM has been developed. The PCM is incorporated whithin the hollow fins of the heat sink and is seen to enhance the heat transfer performance under transient load conditions.

Two heat sink configurations incorporating a metallic alloy PCM (Wood's metal; 50Bi/27Pb/13Sn/10Cd, Melting Point: 70.0oC) are studied: a plate fin heat sink and a pin fin heat sink. Thermal performance enhancements with PCm are experimentally and computationally evaluated. Experiments have been conducted under natural convection conditions, and forced convection studies in a wind tunnel through the range of 0.5 ~ 5 m/s. Constant and periodic thermal inputs from 5 W to 50 W were instantaneously applied using a heater element. Temperature measurements for the heat sinks incorporating PCM show an increased time to reach the maximum-targeted temperature of 90oC, starting from the ambient condition.

Experiments with a fan attached over the heat sinks were also carried out. By measuring the operation time of the fan, energy savings with PCM were found to be in the range of 5.4~12.4%, compared to traditional heat sinks. The measurements show good agreement with computational predictions in three dimensions, using an implicit enthalpy-porosity approach.

Yuang, Lang (M.S. Mechanical Engineering)

The Effect of Orientation and Imposed Circulation on the Performance of A Compact Two-Phase Thermosyphon

This study investigates the issues involved in the design of compact two-phase thermosyphon systems for electronics cooling. In such systems the locations of the evaporator and condenser need to be given a high degree of freedom. So parameters like relative elevation and tubing length must be well studied. For this objective, two thermosyphons with different size of evaporators are designed, built and tested. The key components used in the experiment are: an evaporator enclosure (55 mm x 55 mm x 65 mm, or 20 mm x 20 mm x 20mm internal volume), a simulated chip (base area of 20 mm x 20 mm) with an enhancement structure (10 mm x 10 mm x 6.8 mm). A dielectric coolant (PF-5060, boiling point 56 oC @ 1 atm) is used as the working fluid. Also included in the loop are a natural convection cooled condenser of dimensions 58 mm x 60 mm x 345 mm and connecting tubing. Anticipating situations where gravity does not provide sufficient potential to drive the condensate, pump-assisted circulation loops with a displacement pump (2 - 40 ml/min) are studied. Also, enhancement of boiling heat transfer in compact space is achieved by an enhancement structure having mutually connected microchannels. The relative height between the evaporator and the condenser, the tubing length, the pumping rate, the internal pressure of the loop, the working fluid filling rate, and the heat input were systematically varied. These parameters affect the overall thermal resistance from the chip to the ambient in a complex way. However, close examination of the data suggests that there could be an optimum point in the parametric domain where the thermal resistance is minimized with a least assistance from the pump. The unique contributions of this study are: demonstration of the feasibility of thermosyphon application on electronics cooling independent of gravity; identification of important parameters in thermosyphon design and examination of their effects on the thermosyphon performance, and visualization of the two-phase flow within the thermosyphon loop.