Created: 10/19/99

CALCE EPSC Graduate Student Theses (1999)

Bansal, Dhiraj (M.S. Mechanical Engineering)

Effect of Voids on Electromigration in Solder Bumps for Power Flip Chips

A study of high current induced failures in 63Sn/37Pb eutectic solder bumps and SnAgInCu, lead-free solder bumps is conducted in flip-chip-on-board (FCOB) assemblies. Half of the samples are powered so that a current density of 6100 A/cm2 is maintained through each solder bump and the other half are left unpowered. All the samples are tested at elevated temperature with the junction temperature reaching 150oC in case of the powered samples. Any change in resistance of the samples is monitored in situ, which is used as the failure criteria. Lead-free solder is found to have a longer mean time to failure than its Sn/Pb eutectic solder. The mode of failure is found to be a slow and steady increase in resistance in the case of Sn/Pb eutectic samples as opposed to a sudden electrical open in lead-free samples.

The presence and size of initial voids in the solder bumps do not have any effect on the rate of failures in both the solders. Cross-section and fractographic studies are done on the failed samples to understand the underlying failure mechanism. On the basis of all the observations, hypotheses regarding the exact nature of the failure mechanism are put forward for both the solders. Electromigration effects are found to be more dominant than thermal effects alone in both the solders.

Blattau, Michael Dean (M.S. Mechanical Engineering)

Evaluation of Ist Test Technology for Plated Through Hole Reliability

This research evaluates a new testing method called IST. The evaluation of the Interconnect Stress Test (IST) is accomplished in this thesis by an analysis of data provided by Delphi Delco in which IST was compared to traditional air-air oven testing. A determination of a relationship between the two test methods would allow the replacement of oven testing with IST testing which is faster and more cost effective. Currently, IST is being used as a rapid printed through hole qualification test in which printed wiring board assemblers insure the quality of the interconnections in their supply of multi- layer boards. Since, oven testing is the standard for conducting reliability tests a relationship between oven testing and IST would allow the usage of IST as a reliability test as well. This report introduces one such equation based on the frequency modified Coffin-Manson relationship. Also this report provides background information on IST as well as an electrical- thermal finite element analysis to validate the IST claim of thorough heating and cooling.

Darbha, Krishna (Ph.D. Mechanical Engineering)

A Physics of Failure (PoF) Approach for Virtual Qualification of Area Array Interconnect Technologies

Recent advances in technology, coupled with the relentless drive to remain competitive in world markets, are motivating industries to focus more on product effectiveness and better reliability assessment techniques. The increase in demand for highly reliable electronic assemblies necessitates a physics-of-failure approach, often coupled with accelerated stress tests, to scientifically identify and understand the root-cause failure mechanisms. With increasing robustness of new generation electronic assemblies, the cost and time for conducting accelerated tests as a means of qualification of product reliability increases. In other words, the accelerated testing qualification cost is proportional to product reliability, while the virtual qualification cost is the same irrespective of an increase or decrease in product reliability. Virtual qualification presents a viable alternative to save time and cost, especially as the electronic products become increasingly robust.

Virtual qualification of product reliability involves assessing alternative package design solutions, conducting parametric studies on material properties, package geometry, architecture and application environment, evaluating various design trade-offs by determining the sensitivity of dominant failure mechanisms to the stress drivers, conducting a pareto ranking of dominant failure mechanisms and time to failure, and finally in developing effective accelerated tests and screens. The underlying virtual qualification engine will be robust if it involves an effective stress analysis followed by a damage analysis to predict the life time characteristics with sufficient accuracy. This dissertation focuses on the development of a simplified, quick, accurate methodology for analyzing thermomechanical stress-strain history in complex viscoplastic interconnects for CSPs and DCAs. An existing energy partitioning (EP) damage model will be used to predict the durability of the interconnect assembly.

While the stress analysis methodology itself will be "generic" for different package styles, for the purposes of this dissertation, it will be demonstrated and validated only for CSPs and DCAs with results from conventional finite element models. The stress analysis approach will be modular in nature. The critical regions of the electronic assembly will be modeled using a hierarchical finite element methodology (HFEM) while sub-critical regions will be analyzed using "compact" models. For example, in a DCA the critical solder, furthest from the center of the chip, and immediate surroundings like the chip, board and underfill will be modeled using the HFEM while the sub-critical solders, and its attached chip, board and underfill will be analyzed using compact models. The modules will then be assembled together to obtain the response of the entire structure.

The hierarchical finite element methodology (HFEM) to be developed for critical regions of the surface mount interconnect assembly will be based on variational principles. Using an innovative concept of selective domain localization [Ling, 1997] the critical regions will be locally refined using a hierarchical scheme. Ling implemented this scheme by superposing domains in a Rayleigh-Ritz context to capture large gradients of displacement fields. One of the limitations of Ling's model [Ling, 1997; Darbha et al., 1997] is an excessive use of constraint equations to satisfy continuity between neighboring discrete domains because of the use of nodeless Rayleigh-Ritz degrees of freedom. This limitation poses a computational burden and there is hence a need to develop a model which can achieve significant improvements in computational time. This dissertation will use the concept of selective hierarchical domain localization in a finite element context. Continuity is automatically satisfied between neighboring discrete domains and eliminates the need for constraint equations. This scheme will significantly reduce the computational time and aid in rapid product development. This approach can also capture detailed joint geometries and viscoplastic behavior of solder and underfill.

The non-critical solder interconnects, component, board and/or underfills will be modeled as linear elastic beam elements. Compact models will be generated for analyzing these non-critical elements. These models can be easily assembled with the HFEM to then analyze the entire electronic assembly. Fracture mechanics and creep-fatigue damage models (for example Paris law and energy partitioning model) will serve as a viable tool to predict durability of the selected surface mount interconnect technology. Failure mechanisms of interest are delaminations and solder fatigue and their mutual interactions. Life cycle results obtained from the analytical model will be compared with finite element predictions and accelerated life cycle test data.

The important contributions of this dissertation are: the implementation of a hierarchical localized p-type enhancement scheme for stress analysis of complex assemblies, modeling of interactions between different failure mechanisms and demonstration of a validated virtual qualification methodology for new generations of robust electronic assembly technologies.

Das, Diganta (Ph.D. Mechanical Engineering)

Effect of thermal profile on performance and reliability of microelectronics

The availability of electronic parts rated for operating temperature ranges wider than -40 to 85oC is decreasing as semiconductor manufacturers are driven by commercial applications such as computers and communications. The need for parts rated for wider temperature range is growing for applications such as avionics, military, and automotive electronics, although their market share is insignificant. This dissertation examines how the performance assessment of electronic parts can be integrated into the part selection and management process. It provides for the methods of assessment of part to determine if they are capable of operating in an application when the operating temperature range is wider than the manufacturer-specified operating temperature ranges. Three methods of assessment are developed: namely parameter conformance assessment, stress balancing, and parameter re-characterization.

Stress balancing method of thermal uprating is analogous to power derating of active and passive electronic parts where power consumption is limited at higher temperatures. In stress balancing method, this concept is extended above the manufacturer-specified temperature range. The electrical parameters of the part or the system, which affect the power dissipation of the part, are limited to reduce the power dissipation. Parameter re-characterization method of thermal derating mimics the electrical characterization process of the semiconductor manufacturers. Semiconductor manufacturers use characterization process to establish data sheet specification limits and to determine variations of electrical parameters with respect to various electrical and environmental factors. The re-characterization method works on a limited scope to determine effects of change in temperature using the manufacturers' electrical specifications as baseline.

Dujari, Prateek J. (Ph.D. Mechanical Engineering)

Analysis of Random Vibration on Repetitive Shock and Electrodynamic Shakers for Accelerated Fatigue of Electronic Interconnects

Vibration loads are extensively used for accelerated testing to explore the influence of mechanical cyclic stresses on high cycle fatigue failure mechanisms in electronic assemblies. This study investigates the relative effectiveness of two most commonly available commercial vibration shakers viz. repetitive shock (RS) and electro-dynamic (ED) shakers, in stimulating surface-mount interconnect failure mechanisms under room temperature vibration environment. Schemes are developed to match the excitation loads on the two shakers when conducting accelerated life tests. The approach is illustrated on two different circuit card assemblies (CCAs), to compare the ability of the two shakers to accelerate interconnect fatigue failures. The response analysis is combined with fatigue damage analysis to provide a rational method for comparing the relative effectiveness of random vibration stresses on the two shakers. Experimental verification is provided for two different CCAs.

Analysis of fatigue damage due to vibration requires an efficient scheme for vibration response analysis. A method based on wavelet transforms is developed for predicting the vibration response of structures. The proposed method improves the cost-effectiveness of non-stationary response analysis of structures whose modal frequencies and mode shapes are known, by exploiting the time-frequency localization capability of wavelet transforms to provide non-stationary response information from a single sensor. This represents significant improvement over conventional response analysis techniques which require at least as many sensors as the number of modes considered (assuming the eigen functions of the system are pre-determined). Signal separation capabilities of wavelets are used to obtain the modal contributions of a CCA, from response histories collected with a single sensor. The filtered histories of modal contributions are then used to predict vibration response at any desired location of the structure. As examples, the method is applied to predict the response of electronic circuit card assemblies (CCAs) to simulated periodic and non-stationary excitation. The vibration response analysis of the CCA serves as inputs to the fatigue damage analysis which is compared to the experimental results on the RS and ED platforms to compare the effectiveness of the two platforms for stimulating high cycle fatigue failures in accelerated life tests.

Henry, Mark (M.S. Mechanical Engineering)

Moisture Related Growth Failure Mechanisms of Automotive Assemblies

Contaminant residues from circuit card fabrication processes can react with moisture to form electrolytes, which can carry a small current flow between points of voltage. This phenomen can cause conditions that drive dendritic growth or conductive filament formation. This project focuses on the origin of these contaminates in the assembly process, and develops recommendations for preventing or removing them. In a second phase, faster, more cost-effective "fault-potential" indicator tests will be developed as alternatives to life tests.

Solomon, Rajeev (Ph.D. Mechanical Engineering)

Life Cycle Mismatch Assessment and Obsolescence Management of Electronic Components

An electronic part is defined as obsolete when it cannot be procured in the market from the original manufacturer. The demand for electronic parts that are smaller, lighter, more reliable, and less expensive has led to technological advances in consumer electronics and information technology products. As these commercial sectors of market are drivers of market and technology, profits for manufacturers depend largely on high volume manufacturing catering to these sectors. Manufacturers are finding it increasingly difficult and expensive to maintain their relatively slower moving production lines. More and more manufacturers are dropping out of the less lucrative military component market, which also suffer from higher support cost because of its strict speci-fications, inflexible tests, prescribed documentation, and dependence on maintaining old tech-nology.

The impacts of this trend affect all the low volume complex electronics systems (LVCES) industry, which include the military, aerospace, medical and now the auto-motive industries, primarily because they depend on the ready availability of components for systems that have special environmental requirements and long service lives. A key challenge that these industries face is how to tradeoff between the long development and service life require-ments for systems, and the advan-tages of high tech-nology, high reliability, and low cost offered by the majo-rity of today?s component suppliers, and do so with the under-standing that these compo-nents will most likely become obsolete prior to system end-of-life.

Suppliers and customers of electronic parts cannot directly control availability of components, component design stability, package design stability, manufacturing and assembly processes, and quality and reliability standards. Market and technology changes control all these factors. Suppliers can only control their equipment design process, and control the process by which they select and manage electronic parts for their products.

This dissertation will focus on the drivers for obsolescence of electronic parts, the impact of obsolescence on the supply chain, and will develop a parts management strategy to alleviate the effects of obsolescence. Strategies for identification of obsolete parts will be discussed. Strategies to mitigate obsolescence risks, such as lifetime buys, aftermarket sources, microcircuit emulation, part substitution, reverse engineering, and redesign will be discussed with case studies. Net Present Value (NPV) techniques will be used to determine the optimum point of time for redesign versus a lifetime buy option, based on total minimum cost in an obsolete part situation.

The most important contributions to this thesis are: addressing post-obsolescence resolution alternatives using case studies, developing a parts management process to mitigate obsolescence, and using NPV techniques to determine the optimum year of redesign.

Ramaswamy, Chandrashekhar (Ph.D. Mechanical Engineering)

Compact thermosyphons for passive thermal control of high heat flux electronic components

Liquid cooling has gained acceptance as an efficient thermal management technique for handling high heat dissipation rates (10-100 W/cm2). Indirect liquid cooling, wherein the semiconductor chip is not in direct contact with the cooling liquid, is usually implemented using thermosyphons and heat pipes.

Ramgopal, Uppalapati Venkata (M.S. Mechanical Engineering)

A Case Study Assessment of Electronic Part Manufacturers and Part Families

The part manufacturer's organizational quality system practices affect the quality and integrity of the parts they produce, which in turn influence the level of risk inherent in the use of the parts by the equipment supplier. Data from manufacturer's outgoing quality tests, process capability measurements, and reliability tests can provide information regarding quality and integrity of the part, allowing the equipment supplier to make informed decisions regarding parts selection and management. The use of a manufacturer and part assessment process is one step towards ensuring consistent quality and reliability of the equipment supplier's products. This document presents results and observations from the case study on CALCE and AlliedSignal manufacturer and part assessment processes. Next, the document presents recommended assessment criteria to conduct manufacturer and part assessment from the case study analysis and then evaluates the effectiveness of the methodology using a case study example with actual failure data. In addition, the document provides recommendations on minimum acceptable levels and presents the new revised methodology to quantify the findings from the manufacturer and part assessment processes.

Sun, Ming (Ph.D. Mechanical Engineering)

Lifetime Resistance Models of Electrical Contact and Interconnect

It is anticipated that interconnection reliability is a major concern as critical dimensions of ICs and electronics are scaled down. Reliability physics of interconnect and electrical contact associated with this miniaturization is also of great importance, because the electrical conduction is employed as the most fundamental function of electronics. Failures or degradations of electrical conduction in interconnections due to such operating and environmental factors as operating voltage, mechanical stress, temperature and environment have received considerably large attention, however, emphasis has been placed on individual cases and not on the elucidation of the fundamental reliability physics. This dissertation is mainly concerned with the performance and failure of interconnections associated with various packaging levels during the life cycle. Special consideration will be given to the performance assessment of lifetime electrical resistances (resistance and contact resistance), which are of importance in design, manufacturing and new generation of interconnects and electrical contacts. Based on the theoretical and experimental investigation, lifetime resistance and consecutive insulating film growth models of copper interconnect on submicron silicon and electrical contacts relevant to electronic packaging have been developed and discussed.