Cushing, Michael (Ph.D. Reliability Engineering)
Monte Carlo Reliability Simulations Of An Electrical-Overstress Model Using Symbolic Math Tools
Problem Description. Electrical overstress is a failure mechanism where electrical-power surges, approximately 1 to 4,000 microseconds in duration, cause the junctions of on-chip, circuit-protection semiconductors connected to input/output or power pins of an integrated circuit to catastrophically fail due to localized Joule heating. Electrical overstress is currently an important source of integrated-circuit failures and susceptibility to electrical overstress will continue to increase as device feature sizes decrease. Some integrated-circuit manufacturers and users claim that 60 - 80% of failures are due to electrical overstress and electrostatic discharge events. Electrical-overstress modelers contend that electrical overstress is a major and growing problem due to the lack of systematic analysis tools for electrical-overstress reliability.
Methods Used. A numerical analysis of alternative versions of the leading electrical-overstress model was performed. A probabilistic extension of a leading electrical-overstress model, which will effectively support Monte Carlo simulations with only minor expansions of the modeling assumptions, was developed, evaluated and proposed. A computer-simulation model for probabilistic, electrical-overstress reliability analysis, which employs a time-dependent stress-strength approach, was developed. The simulation and pre- and post-simulation analyses were implemented in Mathematica, a sophisticated, commercially available, computer-based system for doing numerical computing, symbolic manipulation, simulation and graphics.
Results\Conclusions. One conclusion was that the approximation to the leading, power-to-failure model should not be used since the numerical errors incurred may be as large as 29%. Another conclusion was that the probabilistic extension of the leading electrical-overstress model, based on a Mathematica, multidimensional InterpolatingFunction object, is both accurate a factor of 450 to 700 times faster than the numerical-integration algorithm. The electrical-overstress, computer-simulation model calculates the probability distribution for the maximum, hot-spot temperature at the junction in a circuit-protection semiconductor protecting a pair of integrated-circuit pins. Also calculated are the probabilistic stress-strength interference, reliability as a function of the surge sequence, and reliability, probability density and hazard as a function of life-cycle time. The work documented in this dissertation provides an improved capability to perform probabilistic, electrical-overstress reliability analyses. The modules in this dissertation constitute a basis for a formal extension of Mathematica for the purpose of performing electrical-overstress reliability analyses.
Ling, Sharon X. (Ph.D. Mechanical Engineering)
A Multi-domain Rayleigh Ritz Thermomechanical Stress Analysis Model for Surface-mount Interconnects
Effective stress analysis and fatigue analysis methods are essential for proper design and reliability assessment for surface-mount interconnects. A generic Multi-Domain Rayleigh Ritz (MDRR) stress analysis model is developed to perform thermomechanical viscoplastic stress analyses of surface-mount interconnects, in order to obtain the stress and strain fields caused by global and local thermal expansion mismatches. The Rayleigh Ritz potential energy minimization principle is used to obtain the solution based on pre-assumed, multi-field displacements. The solder domain is selectively discretized into colonies of nested sub-domains where large gradients of strain are expected. The number and size of sub-domains within each colony can be varied for optimum accuracy. Potential energy stored in the surface mount assembly is calculated based on the displacement fields. Minimization of the total potential energy provides the solution to the pre-assumed multi-field displacements, resulting in prediction of strain and stress distributions within the solder joint. Load-stepping and/or time-stepping techniques are used to obtain piece-wise linear approximations to the non-linear elasto-plastic and viscoplastic deformation. The stress and strain fields are calculated for each increment and are accumulated throughout the loading and unloading history. The stress-strain hysteresis loop is obtained after the completion of each thermal cycle. Elastic strain energy storage, plastic work dissipation and creep work dissipation are also computed. The energy partitioning fatigue model is applied to estimate fatigue endurance of the solder joint. The comparable accuracy is achieved comparing with finite element technique with only fraction of the computational efforts.
Neel, John (M.S. Mechanical Engineering)
Semi-analytic Durability Models for Surface Mount Solder Joints
With the advent of surface mount technology the role of solder has increased from providing an electrical contact to include the responsibility of providing the only means of mechanical attachment between components and the Printed Wiring Board (PWB). Because solder is now responsible for maintaining a mechanical attachment to the PWB electronic assemblies it now can experience failure by cyclic fatigue from thermal mechanical loading, vibration loading, or a combination of both scenarios. Thermal me chanical fatigue is generally associated with low cycle fatigue, whereas vibration is associated with high cycle fatigue. It has become a crucial part of reliability assessment for the electronic packaging industry to develop models which accurately pred ict solder joint fatigue life.
This study examines fatigue in solder joints due to creep/fatigue crack growth when electronic surface mount components are subjected to thermal cycling. An existing 2-D analytical model for predicting shear stress and shear strain of solder joint assemb lies in leadless components is modified to account for the compliance of leads, and warping in the printed wiring board and component. The model is developed for leadless ceramic chip carriers, and is then extended to incorporate bending mismatches between the component and PWB. Finally, a model which accounts for lead stiffness of various peripherally leaded components is developed. Hysteresis plots are generated for example components and the solder joint fatigue life is estimated using the energy partitioning technique. The results obtained are compared to two dimensional fini te element analysis. Lastly important caveats and insights obtained from working with such semi-analytic durability models are discussed and conclusions presented.
Searls, Damion (M.S. Mechanical Engineering)
Uprating of Components for Use Outside Their Temperature Specifications
Applications such as military or aerospace are often characterized by environments involving temperature extremes. Traditionally, only extended temperature range electronic components (e.g., military range) were used with these applications since it was commonly thought that only these packages could withstand the environments reliably. However, over the past decade, system designers have been under increasing pressure to use components from the lower temperature ranges in their designs. Reasons for this include the vastly greater availability, lower cost, and improved size and weight versus the traditional military components. As a result, many designers have concerns over how narrower temperature range parts will perform in extended temperature environments. This thesis presents a methodology for uprating as one method to address the above concerns. Uprating refers to the process of reducing the risk of using components and/or systems without any design changes outside the manufacturer's environmental limits. This work focuses on temperature as the parameter beyond the manufacturer's specified limit. To assist in addressing the uprating issue, Chapter 2 summarizes CMOS electrical performance at cold temperatures. A discussion of the uprating process follows in Chapter 3. This process involves developing criteria for successful uprating, and understanding issues in performance and reliability, product life cycle, obsolescence, and legal liability. Lastly, Chapter 4 presents a case study of uprating. This example tests the Motorola MC68332 microprocessor for applicability in an environment beyond its manufacturer's specified temperature rating.
To'mey, Hala (M.S. Mechanical Engineering)
Qualification of IBM Laptop for Ruggedized Environment
The introduction of the laptop into the mobile work environment created a need for a unit which could withstand harsh field environment. The need was recognized by Alliant Techsystems, and they hope to capture the market by launching a product quickly. The University of Maryland was contacted for the conceptual design and the final product testing. Instead of designing a completely new product, it was deemed more beneficial to ruggedize commercially available products such as an IBM Thinkpad. Since IBM is a recognized manufacturer of reliable electronic products, the Thinkpad was chosen. The present work addresses the final product testing, and some concerns pertaining to the shock isolation foam layout. The shock isolation foam layout brought forth in the conceptual design could not be used to produce survivability of the final product due to time restraint and the lack of an appropriate prototype for testing. Once a prototype was obtained, different foam configurations were tested in order to determine the optimum configuration. The qualification testing consisted of thermal, vibration, shock and drop testing. The thermal testing validated the functionality of the laptop through a temperature range of -20oC through 60oC. The vibration testing determined the influence of harmonic vibration excitation on the operational integrity of the laptop. The shock test assured that the laptop could withstand the non-repetitive shocks encountered in the service environments. The drop tests were conducted to assure that the laptop could withstand accidental drops from a height of 3 feet. The ruggedized laptop functioned perfectly through all the qualification testing.
Turner, Kellie A. (M.S. Mechanical Engineering)
Uprating the IBM 730TE Thinkpad Computer for use in a Public Safety Mobile Computing Environment
This is an emerging market for portable computers in the public safety sector. In order to capture this market quickly, commercial off the shelf product can be modified for use in this mobile computing environment. If the harsh environment is more severe than the manufacturers specifications allow, the product must be uprated, i.e., the manufacturers product specification limits must be extended. This thesis provides methodologies to obtain reliability information for IBM 730TE Thinkpad computers to be uprated for use in a public safety mobile computing environment. This ruggedized use environment includes wider temperature, vibration, and drop shock specification ranges. In order to uprate this product, accelerated life and drop test were conducted for these new higher specification limits. The thesis introduces methodologies for vibrational and thermal accelerated testing, as well as drop shock testing, with specific application to the IBM units. In addition, the results of the accelerated test and drop test are presented and analyzed for reliability predictions on the expanded specification ranges.
Walker, Donald James (M.S. Mechanical Engineering)
Circuit Card Assembly Failure Mechanism Model Handbook
This research concisely highlights the need for a convenient and practical reference guide for practicing engineers that contains and organizes many of the dominant Circuit Card Assembly (CCA) failure mechanism models. Information about each model is available in the open literature, but archival journal publications are not necessarily easy to find and are usually written in a style that is both dense with information and difficult to understand in a short period of time. A solution is presented in the form of an electronic handbook that exploits the many advantages of the hypertext markup language (HTML) format. The handbook is constructed with hypertext links from one page to many other pages. These hypertext links are a convenient way to allow the information to be presented in a layered and context sensitive way so that the reader can go into as much or as little detail about a model as necessary or desired. In addition to permitting easy comparison between models, links to other pages also allow the inclusion of online calculators that allow the endbook user to perform calculations easily and obtain answers immediately.