IEEE Transactions on Components, Packaging and Manufacturing Technology (Early Access), DOI: https://doi.org/10.1109/TCPMT.2026.3704315

Investigation of the Interface Reliability of Multi-level Stacked Copper Microvias: Modeling and Simulation

Syed Mujahid Abbas^1,2, Qiang Yu¹, and Michael Pecht<sup>3

1</sup>Graduate School of Engineering Sciences, Yokohama National University, Kanagawa, Japan
²Faculty of Mechanical Engineering, NUST, Islamabad, Pakistan
³Center for Advanced Life Cycle Engineering (CALCE), University of Maryland, College Park, MD, USA

For more information about this article and related research, please contact Prof. Michael Pecht.

Abstract:

Microvias serve as electrical interconnections between conducting layers of laminates in high-density interconnect printed circuit boards. However, stacked microvias can interfacially separate or crack due to fatigue if not properly designed and manufactured. In this paper, seven different types of commercially used microvia configurations, e.g., stacked, staggered, semi-stacked, stacked on buried via, and stacked offset to buried vias, are modeled using finite element analysis to investigate the mechanisms of failure. The simulation results strongly correlate with experimental data, and a novel Coffin-Manson factor was developed to predict the fatigue life of the microvia interface. Insights into the interfacial separation and target pad cracking are then presented.

This article is available online here and to CALCE Consortium Members for personal review.