ECS Transactions, Volume: 80, Issue: 7, Pg: 197-201, 2017, DOI: 10.1149/08007.0197ecst

Achieving Vertical Trench-Gate GaN MOSFETs Via Process Optimization

D. I. Shahina, A. Christoua, T.J. Andersonb
a Department of Materials Science and Engineering, University of Maryland, College Park, Maryland 20742, USA
b U.S. Naval Research Laboratory, Washington, DC 20735, USA


Gallium nitride is a strong candidate material for advanced power electronics that exceed the capabilities of current Si and SiC technologies. The ideal device structure for GaN power switches is the vertical metal-oxide-semiconductor field effect transistor (MOSFET). Current vertical GaN MOSFETs have not reached theoretical performance limits. Optimization of these devices is required to improve their performance, particularly with respect to the dielectric/semiconductor interface along the device active regions, and processing used to fabricate the vertical channel regions. We have studied two atomic layer deposition precursor systems for ZrO2 dielectrics on both as-grown and plasma-etched c-plane GaN. Piranha etching of GaN surfaces before ALD improved the capacitance-voltage response of the deposited ZrO2. 5-10 μm deep trenches in GaN substrates have also been fabricated, to allow more detailed study of the trench sidewalls and dielectric interfaces on the etched surfaces before and after hydroxide-based wet etching.

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