IPC APEX EXPO Conference Proceedings, February, 2014

Simulation of the Influence of Manufacturing Quality on Thermomechanical Stress of Microvias

Yan Ning, Michael Azarian, and Michael Pecht

Department of Mechanical Engineering, University of Maryland, College Park, MD 20742, USA

Abstract:

The advancement of area-array packages, such as flip chips and chip scale packages, has driven the adoption of high density interconnects (HDIs) that allow for an increased number of I/Os with a smaller footprint area. HDI substrates and printed circuit boards use microvias as interconnects between conductor layers. HDIs have evolved from single-level microvias to stacked microvias that traverse sequential layers. A stacked microvia is filled with electroplated copper to make electrical interconnections and support the outer level(s) of the microvia or components mounted to the upper capture pad. A common problem in copper-filled microvia fabrication is that the copper plating process can result in incomplete filling, dimples, or voids. However, the effects of these copper filling defects on the reliability of microvias are unknown. This study is the first known investigation and analysis of the influence of voiding and incomplete copper filling defects on the thermomechanical stresses in microvias. Single-level and stacked microvias were modeled using the finite element method to simulate fully filled and partially filled microvias, as well as filled microvias with voids of different sizes. The stress states of these microvia models under thermal shock loads were investigated to determine the effects of the filling defects on the reliability of microvias. The finite element modeling and simulation results demonstrated that stacked microvias experienced greater stresses than single-level microvias. With the same microvia geometry and material properties, copper filling reduced the stress level on the microvia structure, where fully copper-filled microvias had a lower stress level than partially filled microvias. The presence of voids generally increased the stress level in the microvia structure, but with a very small void size, the maximum stress in the microvia can be less than in a non-voided microvia. The stress level and the location of the maximum stress varied with changes in the void size.

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