IEEE Transactions on Device and Materials Reliability, Vol. 9, No. 3, pp. 419-424, September 2009

Warpage Analysis of Flip-Chip PBGA Packages Subject to Thermal Loading

Ming-Yi Tsai
Member, IEEE
Department of Mechanical Engineering,
Chang Gung University
Kwei-Shan 333, Taiwan

Hsing-Yu Chang
Department of Mechanical Engineering, Chang
Gung University, Kwei-Shan 333, Taiwan.
Taiwanese Army, Taiwan

Michael Pecht
Fellow, IEEE
City University of Hong Kong,
Kowloon, Hong Kong,
Electronic Products and Systems Consortium,
Center for Advanced Life Cycle Engineering,
University of Maryland,
College Park, MD, 20742, USA


The aim of this paper was to measure and simulate the warpage of flip-chip PBGA packages subject to thermal loading (from room temperature to 260 ◦C). In the experiments, a full-field shadow moiré was used to measure real-time out-of-plane deformations (warpages) on the substrate and chip surfaces of the flip-chip packages under thermal heating and cooling conditions. A finite-element method (FEM) and Suhir’s die-assembly theory, together with the measured material data (elastic moduli and coefficients of thermal expansion (CTEs) for organic substrates), were used to analyze the thermally induced deformations of the packages to gain insight into their mechanics. The strain gauge data used to determine the CTEs of the substrates also indicated that there was nearly no bending strain under thermal loading. The full-field warpages on the substrate surface of the packages from the shadow moiré were documented under temperature loading. It was also found that there were different zero-warpage temperatures (which resulted in a variation of warpages at room temperature) for the four test packages during thermal loading, but they had similar warpage rates (the slope of warpage with respect to temperature). This might have been due to the creep of the underfill and the solder bumps in the packages at the solder reflow temperature. Regardless of the zero-warpage temperature, the warpage of the packages can be well simulated or predicted by FEM and Suhir’s theory. The key material properties (elastic moduli and CTEs for the substrate and underfill) that affect the maximum warpage of the package were thoroughly studied. It was found that, among these material properties, a low elastic modulus for the underfill can significantly reduce the maximum warpage, while its CTE is much less sensitive to warpage. Moreover, the substrate CTE affects the warpage of a package only with noncompliant underfills, while a typical substrate elastic modulus (ranging from 10 to 30 GPa) is insensitive to warpage, unless its value is lower than a few gigapascals.

Index Terms: Flip-chip PBGA (FCBGA) packages, shadow moiré, simulation, thermal deformation, warpage.

Complete article is available to CALCE Consortium Members.

© IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

[Home Page] [Articles Page]
Copyright � 2008 by CALCE and the University of Maryland, All Rights Reserved