Abstract:

Over the past ten years, two new test methods: Interconnect Stress Test [1] and Highly Accelerated Thermal Shock [2] have been developed to perform thermal cycling testing and in particular, to measure plated through hole reliability. Both of these test methods have proved useful in their ability to quantify plated through hole reliability and have gained a wide level of acceptance and creditability within the industry. Along with more tradition air-to-air and liquid-to-liquid thermal cycle methods, these two new test methods expand the test methods available to the interconnect industry. While the number of testing options for plated through hole thermal cycling has increased, there has been little work performed within the industry on developing methods to analyze and use the data coming from these new test methods.

This paper covers use of IST testing to obtain plated through hole cycle to failure data followed by methods to analyze and plot the data over a wide range of temperatures. In particular, the paper will focus on the use of material properties like the modulus as a function of temperature and the coefficient of thermal expansion as a function of temperature to calculate the stress on a plated through hole versus temperature. In this paper we will also explore the use of the Inverse Power Law (IPL) to analyze the plated through hole stress versus cycle to failure relationship. Once we have used IPL to established the cycle to failure relationship to stress for a given laminate and PCB design, it is then possible to estimate the number of cycles to failure in the field as a function of the number of cycles of assembly stress, the peak assembly temperature, and the maximum temperature in the field.

Keywords: IST, HATS, Lead-Free, CTF, Cycles to Failure, Via Reliability, PTH Reliability

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