Electronics Cooling, Vol. 9, No. 1, pp. 10-14, February 2003

Optical Measurement of Flip-Chip Package Warpage and Its Effect on Thermal Interfaces

Bongtae Han
CALCE Electronic Products and Systems Center
University of Maryland
College Park, MD 20742


Flip chip technology has emerged as an important future chip level package solution to meet the ever-increasing demand of high I/O requirements. The flip chip technology was implemented originally for a multi-layer ceramic substrate. In the ceramic flip chip package, a shear strain in each bump, produced by the mismatch of the coefficient of thermal expansion (CTE) between the chip and the ceramic substrate, was proportional to its distance from the neutral point (DNP). Consequently, the size of the silicon device was limited to prevent solder bumps from premature failure. Recently, an innovative underfill technique was developed and implemented for the flip chip technology to enhance solder bump reliability, where the gaps between the solder bumps were filled with an epoxy encapsulant. The remarkable improvement of solder fatigue provided by the underfill enabled the industry to extend the flip chip technology to organic substrates, leading to the development of the flipchip plastic ball grid array (FC-PBGA) package.

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