Proceedings of the 18th International VLSI Multilevel Interconnection, held in Santa Clara, CA, November 28-29, 2001
University of Maryland
College Park, MD 20742
One of the most time consuming activities in electronics development is reliability assessment and qualification. This is a process to verify whether a product will operate to a specified performance level under actual life cycle loads for some specified length of time. Reliability assessment and qualification is usually accomplished by testing under accelerated loads to achieve time compression. Typical qualification methods have been borrowed from the military, in many cases without knowledge of the rationale or assessment of the true benefits. In fact, prediction of field reliability from these tests has generally been quite poor, and these tests are not optimized for new device technologies such as are present in ULSI electronics. This paper aims to provide a more adaptable approach to reliability assessment, requiring very little time and money, because the process is simulated. This paper presents this methodology and a decision support system developed to facilitate design- for-reliability of microelectronic systems. This system assesses time-to-failure based on models of the fundamental mechanisms by which electronics fail. The unique issues of ULSI device electronics will be discussed.
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