Proceedings of the High-Level Electronic Design Conference, San Jose, CA, pp. 197-204, Oct. 1997

Modeling the Impact of Packaging During High-Level System Design: The Integration of Physical Partition into Virtual Prototyping

P. Stoaks and P. Sandborn


As system designers drive systems to be cheaper, better, faster, and smaller, the impact of packaging decisions on the physical characteristics of the system is growing.  A methodology called System Virtual Prototyping is outlined that brings analysis and optimization of these tradeoffs to the front of the system design process.  The key to this methodology is combining accurate manufacturing information with design information to optimize the system characteristics.  An example, which was analyzed with the SavanSys system virtual prototyping software, is presented.  The example shows how the use of a more expensive micro-via laminate substrate technology can result in a less expensive system than conventional printed wiring board substrate technologies under application specific design conditions.

Complete article is available to CALCE Consortium members.

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