Abstract:

A methodology is proposed for the validation of compact thermal models of electronic packages which utilizes data and simulations obtained from a simple but realistic system containing the package. The test system used to demonstrate the methodology is the enclosure specified by the Electronic Industries Association JEDEC Subcommittee JC15.1 for thermal measurements in a natural convection environment Simulations for a detailed model and several different compact models for a 88-pin plastic quad flat-package in the enclosure are in good agreement with experimental measurements of junction temperature. The study shows that the system -Must be well characterized, including accurate knowledge of circuit board thermal conductivity and accurate simulation of radiation heat transfer, to serve for validation purposes. For the package used in this study, system level considerations can outweigh package level considerations for predicting junction temperature. Given that the system is accurately modeled, the JEDEC enclosure can serve as a viable experimental validation tool for compact models.
 

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