A critical requirement for the conceptual design of electronic modules
is the determination of the number of layers necessary to wire or "route"
a design. The challenge is to successfully estimate the number of layers
before detailed routing is possible. There are several algorithms for estimating
substrate interconnect requirements for a design prior to the existence
of a netlist. Some approaches depend on the use of heuristics derived from
observing actually routed designs, while others depend on geometric arguments.
The use, applicability, and uncertainties associated with the estimation
techniques are not widely understood. In this paper several wiring estimation
algorithms are applied to a variety of products that use printed wiring
board and multichip module technologies. The algorithms considered include
section-crossing, Rent's rule, geometric counting, and statistical wire
article is available to CALCE Consortium Members.