P. Sandborn, C. Palesko, D. Gullickson, and K. Drake
Traditionally electronic system design automation tools have focused on logical and behavioral partitioning and synthesis with little or no formal treatment of the physical implementation of a design. ASICs and other complex ICs are synthesized with relatively little understanding of how they impact the physical construction and performance of the system into which they are inserted (system size, routability, thermal performance, reliability, cost, etc...). Lack of methodologies and tools that enable the physical implementation of systems to be studied and optimized during the planning and specification phase of design is causing a serious disconnect in the design process for high density systems (e.g., PCMCIA cards, MCMs, etc...). In order to meet the demands produced by miniaturization, performance, and market window constraints, designers must adapt their design processes to address the physical implementation of systems as early in the design process as high-level logic design, i.e., “physical synthesis?
This paper discusses the unique problems associated with automating
the determination of the physical implementation of a system during design
planning and specification, and suggests a methodology that addresses design-for-packagability
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