A Thermo-Mechanical Fatigue Analysis Of High Density Interconnect Vias
A. Prabhu, D. Barker, M. Pecht, J. Evans, W. Grieg, E. Bernard and E. Smith
A potential failure mechanism in copper/polymer overlay, high density interconnect technology is via fatigue due to the coefficient of thermal expansion (CTE) mismatch between dielectric materials and the metallization in the via structure. This mismatch generates thermal stresses when the structure is subjected to cyclic temperature loads. A finite element analysis was conducted on a HDI via structure for a representative via (with surrounding dielectric) to determine the effect of accelerated temperature cycling and thermal shock. The results were then utilized to estimate the lower limit of the fatigue life of the via structure. The results are consistent with test data accumulated by Texas Instruments and Naval Surface Weapons Center under the Reliability Technology to Achieve Insertion of Advanced Packaging (RELTECH) program.
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