To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test and whether to apply Design for Test (DFT) and Built-In Self-Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this article we describe a tool called High level Test Economics Advisor (Hi-TEA) that analyzes the economics of various test strategies for multichip design at an early stage of the design cycle. The tool also allows the user to perform trade-off analysis on the impact of various cost, yielf, or test effectiveness parameter on the final cost and quality of mutichip designs. Experimental trade-off analysis data that were generated using the tool for some leading-edge multichip designs will also be presented.
 

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