Module Level Performance Simulator for Electrical and Optical Interconnects
L. Guan, C. Pusarla, G. Halkias, and A. Christou
As speed and complexity of electronic systems increase, the interconnect density has become the critical limitation to the performance of electrical systems. The performance of computing and switching systems can be increased by optimizing the interconnect density and throughput. At the board to board level, electrical interconnects at high speeds require a bulky and expensive backplane . At the chip to chip area, the allocation of interconnects limits the performance of the chips. Electrical glossy lines limit the maximum interconnect distance due to reflections, risetime degradation, increased delay, attenuation and cross talk . Optical interconnects present the possibility of solving the interconnect problems by potentially achieving a high bandwidth and high volume density of channels. At high data rates (greater than 1 Gb/s) several channels may operate with negligible mutual interference.
In computer systems, the various multiprocessor architectures require a large number of interconnects between the processors, peripherals and the main memory. The delay associated with the access to memory presents a major limitation for achieving small signal delays in computer systems . In developing new packaging and interconnect technologies, the recent efforts have concentrated on multi-chip modules (MCM). The proposed architectures are three dimensional assemblies such as die stacks, new electrical interconnect configurations (Tape automated bonding, Flip Chip, Pin Grid Arrays) or new interconnect technologies such as superconducting wires and optical interconnects. Since the interconnect technologies are difficult to assess, a consistent comparison of the performance of the different interconnect technologies is of paramount importance.
In the present investigation, simulated based on existing electrical and optical interconnects have been developed with the objective of simulating the performance of the interconnects and understanding the limitations of each interconnect technology and architecture. For both the electrical and the optical interconnects, the performance of inter-board and inter-chip level links are simulated based on existing electrical and optical components.
Previous interconnect comparative investigations have not examined specific interconnect configurations. Merkelo et al.  have presented various model for optical and electrical interconnects and addressed issues of fanout, damping and dispersion. Without addressing the specific interconnect technologies. Feldman et al.  have carried out a comparative study of electrical and optical interconnects and gave addresses power dissipation and delay of optical interconnects. The switching energy dependence on rise time, fanout and optical link efficiency was calculated. In addition, they have performed simulations to compare the delay for four generic interconnect technologies. Their work however cannot model complicated packaging configurations, and thus cannot be applied to assess the performance of the various architectures presently under development.
The objective of the present investigation was to develop a CAD framework for the comprehensive understanding of the performance of the optical and electrical interconnects. The key issues related to performance and manufacturing differences between optical and electrical interconnects are investigated through the development and application of user friendly software modules.
In this paper we describe the computer model developed for the evaluation
of the performance of the electrical and optical interconnects. Critical
parameters describing performance were simulated for specific interconnect
architectures (electrical and optical) in order to test the ability of
the model to address real interconnect problems for specific technologies