13th IEEE/CHMT International Electronics Manuf. Technology Sym., Baltimore, MD, pp. 19-29, Sept. 28-30, 1992
A. Dasgupta, S. Verma, and R. Agarwal
University of Maryland
College Park, MD 20742
This paper discusses the importance of scientific product validation,
process verification and control, as essential subtasks in an integrated
QML approach to reliable electronic packaging. The distinctions between
product validation and process verification functions are defines. A generic
and unified approach is presented for product validation tasks. The role
of analysis, simulation and testing in design model development and product
validation is qualitatively discussed. Tools are presents to hierarchize
the influence of the various design and manufacturing variable on product
reliability, quality, yield and life-cycle cost. Case studies are presented
to illustrate applications of the main concepts.
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